Searched hist:d5ac6eef91965b519d8f15f17febfa0ea2ee0adc (Results 1 – 2 of 2) sorted by relevance
| /rk3399_rockchip-uboot/arch/arm/mach-sunxi/ |
| H A D | clock_sun6i.c | d5ac6eef91965b519d8f15f17febfa0ea2ee0adc Fri Aug 19 11:40:46 UTC 2016 Jens Kuske <jenskuske@gmail.com> sunxi: Tune H3 DRAM PLL to improve lock time
The H3 PLL5 used for DRAM barely manages to lock to the required
frequency before DRAM controller starts, sometimes leading to wrong
delay-line calibration results.
This patch changes the PLL tuning parameters to the same values as
boot0 used, which speeds up the locking and fixes the problem.
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-sunxi/ |
| H A D | clock_sun6i.h | d5ac6eef91965b519d8f15f17febfa0ea2ee0adc Fri Aug 19 11:40:46 UTC 2016 Jens Kuske <jenskuske@gmail.com> sunxi: Tune H3 DRAM PLL to improve lock time
The H3 PLL5 used for DRAM barely manages to lock to the required
frequency before DRAM controller starts, sometimes leading to wrong
delay-line calibration results.
This patch changes the PLL tuning parameters to the same values as
boot0 used, which speeds up the locking and fixes the problem.
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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