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H A Dap.hd0edce4fa394325a0ccfd38a5d668fb5ee1af34d Mon Mar 25 23:22:26 UTC 2013 Tom Warren <twarren@nvidia.com> Tegra: Configure L2 cache control reg properly.

Without this change, kernel fails at calling function cache_clean_flush
during kernel early boot.

Aprocryphally, intended for T114 only, so I check for a T114 SoC.
Works (i.e. dalmore 3.8 kernel now starts printing to console).

Signed-off-by: Tom Warren <twarren@nvidia.com>