Searched hist:cb55615c506d6bff3f1a9223182e190abbbf6fc5 (Results 1 – 2 of 2) sorted by relevance
| /rk3399_ARM-atf/include/lib/el3_runtime/aarch64/ |
| H A D | context.h | cb55615c506d6bff3f1a9223182e190abbbf6fc5 Tue Jul 28 06:22:30 UTC 2020 Manish V Badarkhe <Manish.Badarkhe@arm.com> el3_runtime: Rearrange context offset of EL1 sys registers
SCTLR and TCR registers of EL1 plays role in enabling/disabling of
page table walk for lower ELs (EL0 and EL1).
Hence re-arranged EL1 context offsets to have SCTLR and TCR registers
values one after another in the stack so that these registers values
can be saved and restored using stp and ldp instruction respectively.
Change-Id: Iaa28fd9eba82a60932b6b6d85ec8857a9acd5f8b
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| /rk3399_ARM-atf/lib/el3_runtime/aarch64/ |
| H A D | context.S | cb55615c506d6bff3f1a9223182e190abbbf6fc5 Tue Jul 28 06:22:30 UTC 2020 Manish V Badarkhe <Manish.Badarkhe@arm.com> el3_runtime: Rearrange context offset of EL1 sys registers
SCTLR and TCR registers of EL1 plays role in enabling/disabling of
page table walk for lower ELs (EL0 and EL1).
Hence re-arranged EL1 context offsets to have SCTLR and TCR registers
values one after another in the stack so that these registers values
can be saved and restored using stp and ldp instruction respectively.
Change-Id: Iaa28fd9eba82a60932b6b6d85ec8857a9acd5f8b
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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