Searched hist:ca9286c68a8fe408912fc1cd1b1e1789339ce135 (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/plat/rockchip/rk3399/drivers/pmu/ |
| H A D | m0_ctl.h | ca9286c68a8fe408912fc1cd1b1e1789339ce135 Mon Dec 12 07:18:08 UTC 2016 Lin Huang <hl@rock-chips.com> rockchip: rk3399: improve the m0 enable flow
This patch do following things:
1. Request hresetn_cm0s_pmu_req first then request
poresetn_cm0s_pmu_req during M0 enable.
2. Do not diable M0 clock for ddr dvfs.
3. Correct the clk_pmum0_gating_dis bit, it is BIT0 not BIT1
4. do not set/clear hclk_noc_pmu_en in M0 code, it does not relate
to the M0 clock.
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
|
| H A D | m0_ctl.c | ca9286c68a8fe408912fc1cd1b1e1789339ce135 Mon Dec 12 07:18:08 UTC 2016 Lin Huang <hl@rock-chips.com> rockchip: rk3399: improve the m0 enable flow
This patch do following things:
1. Request hresetn_cm0s_pmu_req first then request
poresetn_cm0s_pmu_req during M0 enable.
2. Do not diable M0 clock for ddr dvfs.
3. Correct the clk_pmum0_gating_dis bit, it is BIT0 not BIT1
4. do not set/clear hclk_noc_pmu_en in M0 code, it does not relate
to the M0 clock.
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
|
| H A D | pmu.c | ca9286c68a8fe408912fc1cd1b1e1789339ce135 Mon Dec 12 07:18:08 UTC 2016 Lin Huang <hl@rock-chips.com> rockchip: rk3399: improve the m0 enable flow
This patch do following things:
1. Request hresetn_cm0s_pmu_req first then request
poresetn_cm0s_pmu_req during M0 enable.
2. Do not diable M0 clock for ddr dvfs.
3. Correct the clk_pmum0_gating_dis bit, it is BIT0 not BIT1
4. do not set/clear hclk_noc_pmu_en in M0 code, it does not relate
to the M0 clock.
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
|
| /rk3399_ARM-atf/plat/rockchip/rk3399/drivers/dram/ |
| H A D | dfs.c | ca9286c68a8fe408912fc1cd1b1e1789339ce135 Mon Dec 12 07:18:08 UTC 2016 Lin Huang <hl@rock-chips.com> rockchip: rk3399: improve the m0 enable flow
This patch do following things:
1. Request hresetn_cm0s_pmu_req first then request
poresetn_cm0s_pmu_req during M0 enable.
2. Do not diable M0 clock for ddr dvfs.
3. Correct the clk_pmum0_gating_dis bit, it is BIT0 not BIT1
4. do not set/clear hclk_noc_pmu_en in M0 code, it does not relate
to the M0 clock.
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
|