Searched hist:c833ca66a6fecbc54e038164e466be677559ec4e (Results 1 – 3 of 3) sorted by relevance
| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cortex_x4.S | c833ca66a6fecbc54e038164e466be677559ec4e Wed Apr 10 20:33:21 UTC 2024 Bipin Ravi <bipin.ravi@arm.com> fix(cpus): workaround for Cortex-X4 erratum 2740089
Cortex-X4 erratum 2740089 is a Cat B erratum that applies to
all revisions <=r0p1 and is fixed in r0p2. The workaround is to
insert a dsb before the isb in the power down sequence.
SDEN documentation:
https://developer.arm.com/documentation/SDEN2432808/latest
Change-Id: I1d0fa4dd383437044a4467591f65a4a8514cabdc
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
|
| /rk3399_ARM-atf/docs/design/ |
| H A D | cpu-specific-build-macros.rst | c833ca66a6fecbc54e038164e466be677559ec4e Wed Apr 10 20:33:21 UTC 2024 Bipin Ravi <bipin.ravi@arm.com> fix(cpus): workaround for Cortex-X4 erratum 2740089
Cortex-X4 erratum 2740089 is a Cat B erratum that applies to
all revisions <=r0p1 and is fixed in r0p2. The workaround is to
insert a dsb before the isb in the power down sequence.
SDEN documentation:
https://developer.arm.com/documentation/SDEN2432808/latest
Change-Id: I1d0fa4dd383437044a4467591f65a4a8514cabdc
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
|
| /rk3399_ARM-atf/lib/cpus/ |
| H A D | cpu-ops.mk | c833ca66a6fecbc54e038164e466be677559ec4e Wed Apr 10 20:33:21 UTC 2024 Bipin Ravi <bipin.ravi@arm.com> fix(cpus): workaround for Cortex-X4 erratum 2740089
Cortex-X4 erratum 2740089 is a Cat B erratum that applies to
all revisions <=r0p1 and is fixed in r0p2. The workaround is to
insert a dsb before the isb in the power down sequence.
SDEN documentation:
https://developer.arm.com/documentation/SDEN2432808/latest
Change-Id: I1d0fa4dd383437044a4467591f65a4a8514cabdc
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
|