Searched hist:c82e9de400ee36038c76be67c5a6fb39c165ac1c (Results 1 – 2 of 2) sorted by relevance
| /rk3399_rockchip-uboot/doc/ |
| H A D | README.fsl-esdhc | c82e9de400ee36038c76be67c5a6fb39c165ac1c Fri Sep 05 05:52:39 UTC 2014 Wang Huan <b18965@freescale.com> esdhc: Add CONFIG_SYS_FSL_ESDHC_LE and CONFIG_SYS_FSL_ESDHC_BE macros
For LS102xA, the processor is in little-endian mode, while esdhc IP is
in big-endian mode. CONFIG_SYS_FSL_ESDHC_LE and CONFIG_SYS_FSL_ESDHC_BE
are added. So accessing ESDHC registers can be determined by ESDHC IP's
endian mode.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
|
| /rk3399_rockchip-uboot/include/ |
| H A D | fsl_esdhc.h | c82e9de400ee36038c76be67c5a6fb39c165ac1c Fri Sep 05 05:52:39 UTC 2014 Wang Huan <b18965@freescale.com> esdhc: Add CONFIG_SYS_FSL_ESDHC_LE and CONFIG_SYS_FSL_ESDHC_BE macros
For LS102xA, the processor is in little-endian mode, while esdhc IP is
in big-endian mode. CONFIG_SYS_FSL_ESDHC_LE and CONFIG_SYS_FSL_ESDHC_BE
are added. So accessing ESDHC registers can be determined by ESDHC IP's
endian mode.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
|