Searched hist:c6d4705f41d4e45e8cecc6e08b0b89df1ffe57ef (Results 1 – 3 of 3) sorted by relevance
| /rk3399_rockchip-uboot/arch/x86/cpu/quark/ |
| H A D | dram.c | c6d4705f41d4e45e8cecc6e08b0b89df1ffe57ef Mon Sep 14 07:07:41 UTC 2015 Bin Meng <bmeng.cn@gmail.com> x86: quark: Configure MTRR to enable cache
Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs
are accessed indirectly via the message port and not the traditional
MSR mechanism. Only UC, WT and WB cache types are supported.
We configure all the fixed range MTRRs with common values (VGA RAM
as UC, others as WB) and 3 variable range MTRRs for ROM/eSRAM/RAM as
WB, which significantly improves the boot time performance.
With this commit, it takes only 2 seconds for U-Boot to boot to shell
on Intel Galileo board. Previously it took about 6 seconds.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
|
| H A D | quark.c | c6d4705f41d4e45e8cecc6e08b0b89df1ffe57ef Mon Sep 14 07:07:41 UTC 2015 Bin Meng <bmeng.cn@gmail.com> x86: quark: Configure MTRR to enable cache
Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs
are accessed indirectly via the message port and not the traditional
MSR mechanism. Only UC, WT and WB cache types are supported.
We configure all the fixed range MTRRs with common values (VGA RAM
as UC, others as WB) and 3 variable range MTRRs for ROM/eSRAM/RAM as
WB, which significantly improves the boot time performance.
With this commit, it takes only 2 seconds for U-Boot to boot to shell
on Intel Galileo board. Previously it took about 6 seconds.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
|
| /rk3399_rockchip-uboot/arch/x86/include/asm/arch-quark/ |
| H A D | quark.h | c6d4705f41d4e45e8cecc6e08b0b89df1ffe57ef Mon Sep 14 07:07:41 UTC 2015 Bin Meng <bmeng.cn@gmail.com> x86: quark: Configure MTRR to enable cache
Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs
are accessed indirectly via the message port and not the traditional
MSR mechanism. Only UC, WT and WB cache types are supported.
We configure all the fixed range MTRRs with common values (VGA RAM
as UC, others as WB) and 3 variable range MTRRs for ROM/eSRAM/RAM as
WB, which significantly improves the boot time performance.
With this commit, it takes only 2 seconds for U-Boot to boot to shell
on Intel Galileo board. Previously it took about 6 seconds.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
|