Searched hist:c3d0b15de7ece03f0b84b1d15379345b31674a61 (Results 1 – 4 of 4) sorted by relevance
| /optee_os/core/arch/arm/kernel/ |
| H A D | arm32_gicv3_sysreg.txt | c3d0b15de7ece03f0b84b1d15379345b31674a61 Fri Aug 17 08:03:34 UTC 2018 Jens Wiklander <jens.wiklander@linaro.org> core: arm32: generate gicv3 register access code
Replaces the hand crafted system register code in <arm32.h> with
generated code based on arm32_gicv3_sysreg.txt which is extracted from
The ARM Generic Interrupt Controller Architecture Specification GIC
architecture version 3.0 and version 4.0.
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| /optee_os/core/arch/arm/include/ |
| H A D | arm32_macros.S | c3d0b15de7ece03f0b84b1d15379345b31674a61 Fri Aug 17 08:03:34 UTC 2018 Jens Wiklander <jens.wiklander@linaro.org> core: arm32: generate gicv3 register access code
Replaces the hand crafted system register code in <arm32.h> with
generated code based on arm32_gicv3_sysreg.txt which is extracted from
The ARM Generic Interrupt Controller Architecture Specification GIC
architecture version 3.0 and version 4.0.
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
|
| H A D | arm32.h | c3d0b15de7ece03f0b84b1d15379345b31674a61 Fri Aug 17 08:03:34 UTC 2018 Jens Wiklander <jens.wiklander@linaro.org> core: arm32: generate gicv3 register access code
Replaces the hand crafted system register code in <arm32.h> with
generated code based on arm32_gicv3_sysreg.txt which is extracted from
The ARM Generic Interrupt Controller Architecture Specification GIC
architecture version 3.0 and version 4.0.
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
|
| /optee_os/core/arch/arm/ |
| H A D | arm.mk | c3d0b15de7ece03f0b84b1d15379345b31674a61 Fri Aug 17 08:03:34 UTC 2018 Jens Wiklander <jens.wiklander@linaro.org> core: arm32: generate gicv3 register access code
Replaces the hand crafted system register code in <arm32.h> with
generated code based on arm32_gicv3_sysreg.txt which is extracted from
The ARM Generic Interrupt Controller Architecture Specification GIC
architecture version 3.0 and version 4.0.
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
|