Searched hist:c0a4e6b889a702cc2c8375619ce7b093f6b3b1de (Results 1 – 3 of 3) sorted by relevance
| /rk3399_rockchip-uboot/drivers/pci/ |
| H A D | fsl_pci_init.c | c0a4e6b889a702cc2c8375619ce7b093f6b3b1de Mon Nov 26 23:49:45 UTC 2012 Yuanquan Chen <B41889@freescale.com> powerpc/p4080ds: fix PCI-e x8 link training down failure
Due to SerDes configuration error, if we set the PCI-e controller link width
as x8 in RCW and add a narrower width(such as x4, x2 or x1) PCI-e device to
PCI-e slot, it fails to train down to the PCI-e device's link width. According
to p4080ds errata PCIe-A003, we reset the PCI-e controller link width to x4 in
u-boot. Then it can train down to x2 or x1 width to make the PCI-e link between
RC and EP.
Signed-off-by: Yuanquan Chen <B41889@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
| /rk3399_rockchip-uboot/arch/powerpc/cpu/mpc85xx/ |
| H A D | cmd_errata.c | c0a4e6b889a702cc2c8375619ce7b093f6b3b1de Mon Nov 26 23:49:45 UTC 2012 Yuanquan Chen <B41889@freescale.com> powerpc/p4080ds: fix PCI-e x8 link training down failure
Due to SerDes configuration error, if we set the PCI-e controller link width
as x8 in RCW and add a narrower width(such as x4, x2 or x1) PCI-e device to
PCI-e slot, it fails to train down to the PCI-e device's link width. According
to p4080ds errata PCIe-A003, we reset the PCI-e controller link width to x4 in
u-boot. Then it can train down to x2 or x1 width to make the PCI-e link between
RC and EP.
Signed-off-by: Yuanquan Chen <B41889@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
| /rk3399_rockchip-uboot/arch/powerpc/include/asm/ |
| H A D | config_mpc85xx.h | c0a4e6b889a702cc2c8375619ce7b093f6b3b1de Mon Nov 26 23:49:45 UTC 2012 Yuanquan Chen <B41889@freescale.com> powerpc/p4080ds: fix PCI-e x8 link training down failure
Due to SerDes configuration error, if we set the PCI-e controller link width
as x8 in RCW and add a narrower width(such as x4, x2 or x1) PCI-e device to
PCI-e slot, it fails to train down to the PCI-e device's link width. According
to p4080ds errata PCIe-A003, we reset the PCI-e controller link width to x4 in
u-boot. Then it can train down to x2 or x1 width to make the PCI-e link between
RC and EP.
Signed-off-by: Yuanquan Chen <B41889@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|