Searched hist:ba9e6a342de0a8922d75559bc3c539a5174e2004 (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/lib/extensions/pmuv3/aarch64/ |
| H A D | pmuv3.c | ba9e6a342de0a8922d75559bc3c539a5174e2004 Tue Apr 08 13:07:55 UTC 2025 Andre Przywara <andre.przywara@arm.com> feat(cpufeat): add support for PMUv3p9
Armv8.9 introduced the FEAT_PMUV3P9 extension, which allows finer
grained control over EL0 usage of PMU registers. This is controlled by
the new PMUACR_EL1 system register, access to which is guarded by the
MDCR_EL3.EnPM2 bit. We should set this bit to avoid a trap into EL3 when
lower ELs access this register.
Add the required bits and pieces to make this feature usable:
- Add the CPUID and MDCR_EL3 bit definitions associated with
FEAT_PMUV3P9.
- Extend the existing PMU feature check to allow v9 now as well. This
is fine since we don't context switch PMU registers at all, so we
don't need to do much except to flip the MDCR bit:
- Set the EnPM2 bit in pmuv3_enable, so the feature is usuable in
non-secure world (and there only).
- Handle the MDCR bit for the ARCH_FEATURE_AVAILABILITY feature.
Please note that MDCR_EL3.EnPM2 guards other system registers as well,
for other PMU related new architecture features.
Change-Id: I288ca15f5c9efd336c64477d1c6fe9543613e238
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
|
| /rk3399_ARM-atf/include/services/ |
| H A D | arm_arch_svc.h | ba9e6a342de0a8922d75559bc3c539a5174e2004 Tue Apr 08 13:07:55 UTC 2025 Andre Przywara <andre.przywara@arm.com> feat(cpufeat): add support for PMUv3p9
Armv8.9 introduced the FEAT_PMUV3P9 extension, which allows finer
grained control over EL0 usage of PMU registers. This is controlled by
the new PMUACR_EL1 system register, access to which is guarded by the
MDCR_EL3.EnPM2 bit. We should set this bit to avoid a trap into EL3 when
lower ELs access this register.
Add the required bits and pieces to make this feature usable:
- Add the CPUID and MDCR_EL3 bit definitions associated with
FEAT_PMUV3P9.
- Extend the existing PMU feature check to allow v9 now as well. This
is fine since we don't context switch PMU registers at all, so we
don't need to do much except to flip the MDCR bit:
- Set the EnPM2 bit in pmuv3_enable, so the feature is usuable in
non-secure world (and there only).
- Handle the MDCR bit for the ARCH_FEATURE_AVAILABILITY feature.
Please note that MDCR_EL3.EnPM2 guards other system registers as well,
for other PMU related new architecture features.
Change-Id: I288ca15f5c9efd336c64477d1c6fe9543613e238
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
|
| /rk3399_ARM-atf/common/ |
| H A D | feat_detect.c | ba9e6a342de0a8922d75559bc3c539a5174e2004 Tue Apr 08 13:07:55 UTC 2025 Andre Przywara <andre.przywara@arm.com> feat(cpufeat): add support for PMUv3p9
Armv8.9 introduced the FEAT_PMUV3P9 extension, which allows finer
grained control over EL0 usage of PMU registers. This is controlled by
the new PMUACR_EL1 system register, access to which is guarded by the
MDCR_EL3.EnPM2 bit. We should set this bit to avoid a trap into EL3 when
lower ELs access this register.
Add the required bits and pieces to make this feature usable:
- Add the CPUID and MDCR_EL3 bit definitions associated with
FEAT_PMUV3P9.
- Extend the existing PMU feature check to allow v9 now as well. This
is fine since we don't context switch PMU registers at all, so we
don't need to do much except to flip the MDCR bit:
- Set the EnPM2 bit in pmuv3_enable, so the feature is usuable in
non-secure world (and there only).
- Handle the MDCR bit for the ARCH_FEATURE_AVAILABILITY feature.
Please note that MDCR_EL3.EnPM2 guards other system registers as well,
for other PMU related new architecture features.
Change-Id: I288ca15f5c9efd336c64477d1c6fe9543613e238
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
|
| /rk3399_ARM-atf/include/arch/aarch64/ |
| H A D | arch.h | ba9e6a342de0a8922d75559bc3c539a5174e2004 Tue Apr 08 13:07:55 UTC 2025 Andre Przywara <andre.przywara@arm.com> feat(cpufeat): add support for PMUv3p9
Armv8.9 introduced the FEAT_PMUV3P9 extension, which allows finer
grained control over EL0 usage of PMU registers. This is controlled by
the new PMUACR_EL1 system register, access to which is guarded by the
MDCR_EL3.EnPM2 bit. We should set this bit to avoid a trap into EL3 when
lower ELs access this register.
Add the required bits and pieces to make this feature usable:
- Add the CPUID and MDCR_EL3 bit definitions associated with
FEAT_PMUV3P9.
- Extend the existing PMU feature check to allow v9 now as well. This
is fine since we don't context switch PMU registers at all, so we
don't need to do much except to flip the MDCR bit:
- Set the EnPM2 bit in pmuv3_enable, so the feature is usuable in
non-secure world (and there only).
- Handle the MDCR bit for the ARCH_FEATURE_AVAILABILITY feature.
Please note that MDCR_EL3.EnPM2 guards other system registers as well,
for other PMU related new architecture features.
Change-Id: I288ca15f5c9efd336c64477d1c6fe9543613e238
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
|