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| H A D | clk_rk3288.c | b6e52402c4623753f3761c6c8d43016be50aeb88 Wed Sep 20 06:28:19 UTC 2017 David Wu <david.wu@rock-chips.com> rockchip: clk: Add SARADC clock support for rk3288
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.
Change-Id: Icb41bbf2a719ab7b2c1c70e1227408d3abb625db
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
(cherry picked from commit ef4cf5ae393e4adf532f536d6da97c87f88db230)
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