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/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rk3288.cb2259b20377dc9475cb602dd473cf125e519e6af Mon May 15 06:07:09 UTC 2017 Ziyuan Xu <xzy.xu@rock-chips.com> rockchip: clk: rk3288: fix mmc clock setting

Mmc clock automatically divide 2 in internal.

Before this:
gpll = 594MHz, clock = 148.5MHz
div = 594/148.5-1 = 3
output clock is 99MHz

After this:
gpll = 594MHz, clock = 148.5MHz
div = 297+148.5-1/148.5 = 2
output clock is 148.5Mhz

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>