Searched hist:af2536088e2feae2cf1274f48376e3310e0f709e (Results 1 – 3 of 3) sorted by relevance
| /rk3399_rockchip-uboot/board/freescale/p1022ds/ |
| H A D | tlb.c | af2536088e2feae2cf1274f48376e3310e0f709e Fri May 18 06:04:17 UTC 2012 Matthew McClintock <msm@freescale.com> powerpc/p1022ds: add support for SPI and SD boot
Add TLB mappings, board target options, and configuration items
need for SPI/SD boot.
Since P1022DS RevB board, the NOR flash have been changed to 16 bit/28bit
address flash, therefore, when SDHC/ESPI booting and access to eLBC,
the PMUXCR[0~1] must be set to 10b, and PMUXCR[9~10] must be set to
00b for them.
Configure the PX_BRDCFG0[0~1] to 10b which is connected to
SPI devices as SPI_CS(0:3)_B.
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Jiang Yutang <b14898@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
| H A D | p1022ds.c | af2536088e2feae2cf1274f48376e3310e0f709e Fri May 18 06:04:17 UTC 2012 Matthew McClintock <msm@freescale.com> powerpc/p1022ds: add support for SPI and SD boot
Add TLB mappings, board target options, and configuration items
need for SPI/SD boot.
Since P1022DS RevB board, the NOR flash have been changed to 16 bit/28bit
address flash, therefore, when SDHC/ESPI booting and access to eLBC,
the PMUXCR[0~1] must be set to 10b, and PMUXCR[9~10] must be set to
00b for them.
Configure the PX_BRDCFG0[0~1] to 10b which is connected to
SPI devices as SPI_CS(0:3)_B.
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Jiang Yutang <b14898@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
| /rk3399_rockchip-uboot/include/configs/ |
| H A D | P1022DS.h | af2536088e2feae2cf1274f48376e3310e0f709e Fri May 18 06:04:17 UTC 2012 Matthew McClintock <msm@freescale.com> powerpc/p1022ds: add support for SPI and SD boot
Add TLB mappings, board target options, and configuration items
need for SPI/SD boot.
Since P1022DS RevB board, the NOR flash have been changed to 16 bit/28bit
address flash, therefore, when SDHC/ESPI booting and access to eLBC,
the PMUXCR[0~1] must be set to 10b, and PMUXCR[9~10] must be set to
00b for them.
Configure the PX_BRDCFG0[0~1] to 10b which is connected to
SPI devices as SPI_CS(0:3)_B.
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Jiang Yutang <b14898@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|