Searched hist:aee2f33a675891f660fc0d06e739ce85f3472075 (Results 1 – 3 of 3) sorted by relevance
| /rk3399_ARM-atf/plat/ti/k3/board/j784s4/ |
| H A D | board.mk | aee2f33a675891f660fc0d06e739ce85f3472075 Tue Jan 10 19:14:37 UTC 2023 Andrew Davis <afd@ti.com> feat(ti): set L2 cache data ram latency on A72 cores to 4 cycles
The Cortex-A72 based cores on K3 platforms can be clocked fast
enough that an extra latency cycle is needed to ensure correct
L2 access. Set the latency here for all A72 cores.
Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I639091dd0d2de09572bf0f73ac404e306e336883
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| /rk3399_ARM-atf/include/lib/cpus/aarch32/ |
| H A D | cortex_a72.h | aee2f33a675891f660fc0d06e739ce85f3472075 Tue Jan 10 19:14:37 UTC 2023 Andrew Davis <afd@ti.com> feat(ti): set L2 cache data ram latency on A72 cores to 4 cycles
The Cortex-A72 based cores on K3 platforms can be clocked fast
enough that an extra latency cycle is needed to ensure correct
L2 access. Set the latency here for all A72 cores.
Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I639091dd0d2de09572bf0f73ac404e306e336883
|
| /rk3399_ARM-atf/include/lib/cpus/aarch64/ |
| H A D | cortex_a72.h | aee2f33a675891f660fc0d06e739ce85f3472075 Tue Jan 10 19:14:37 UTC 2023 Andrew Davis <afd@ti.com> feat(ti): set L2 cache data ram latency on A72 cores to 4 cycles
The Cortex-A72 based cores on K3 platforms can be clocked fast
enough that an extra latency cycle is needed to ensure correct
L2 access. Set the latency here for all A72 cores.
Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I639091dd0d2de09572bf0f73ac404e306e336883
|