Searched hist:acf3f8da98fdd432a7b0bbcc8c94d706f1bb5c72 (Results 1 – 3 of 3) sorted by relevance
| /rk3399_rockchip-uboot/arch/powerpc/cpu/mpc85xx/ |
| H A D | release.S | acf3f8da98fdd432a7b0bbcc8c94d706f1bb5c72 Thu Jul 21 05:20:21 UTC 2011 Kumar Gala <galak@kernel.crashing.org> powerpc/85xx: Handle the lack of L2 cache on P2040/P2040E
The P2040/P2040E have no L2 cache. So we utilize the SVR to determine
if we are one of these devices and skip the L2 init code in cpu_init.c
and release. For the device tree we skip the updating of the L2 cache
properties but we still update the chain of caches so the CPC/L3 node
can be properly updated.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| H A D | fdt.c | acf3f8da98fdd432a7b0bbcc8c94d706f1bb5c72 Thu Jul 21 05:20:21 UTC 2011 Kumar Gala <galak@kernel.crashing.org> powerpc/85xx: Handle the lack of L2 cache on P2040/P2040E
The P2040/P2040E have no L2 cache. So we utilize the SVR to determine
if we are one of these devices and skip the L2 init code in cpu_init.c
and release. For the device tree we skip the updating of the L2 cache
properties but we still update the chain of caches so the CPC/L3 node
can be properly updated.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| H A D | cpu_init.c | acf3f8da98fdd432a7b0bbcc8c94d706f1bb5c72 Thu Jul 21 05:20:21 UTC 2011 Kumar Gala <galak@kernel.crashing.org> powerpc/85xx: Handle the lack of L2 cache on P2040/P2040E
The P2040/P2040E have no L2 cache. So we utilize the SVR to determine
if we are one of these devices and skip the L2 init code in cpu_init.c
and release. For the device tree we skip the updating of the L2 cache
properties but we still update the chain of caches so the CPC/L3 node
can be properly updated.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|