Searched hist:aba11d4476b56eb7712184597eb303ae544f0c69 (Results 1 – 2 of 2) sorted by relevance
| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-tegra124/ |
| H A D | clock.h | aba11d4476b56eb7712184597eb303ae544f0c69 Tue Sep 08 09:38:03 UTC 2015 Thierry Reding <treding@nvidia.com> ARM: tegra124: Clear IDDQ when enabling PLLC
Enabling a PLL while IDDQ is high. The Linux kernel checks for this
condition and warns about it verbosely, so while this seems to work
fine, fix it up according to the programming guidelines provided in
the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup
Sequence").
Reported-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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| /rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra124/ |
| H A D | clock.c | aba11d4476b56eb7712184597eb303ae544f0c69 Tue Sep 08 09:38:03 UTC 2015 Thierry Reding <treding@nvidia.com> ARM: tegra124: Clear IDDQ when enabling PLLC
Enabling a PLL while IDDQ is high. The Linux kernel checks for this
condition and warns about it verbosely, so while this seems to work
fine, fix it up according to the programming guidelines provided in
the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup
Sequence").
Reported-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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