Searched hist:ab875342e1e6f7af8aa53d242296d185f456d838 (Results 1 – 4 of 4) sorted by relevance
| /optee_os/core/arch/arm/plat-rcar/ |
| H A D | sub.mk | ab875342e1e6f7af8aa53d242296d185f456d838 Thu Feb 10 00:29:45 UTC 2022 Volodymyr Babchuk <volodymyr_babchuk@epam.com> plar: rcar: add initial support for Gen4
RCar Gen4 is the next generation of Renesas automotive
chips. Currently only RCar S4 on board Spider is available. This
platform has 8 CortexA55 cores with GICv3.
This is patch adds minimal support, so not all Gen4 features are
available. Namely, ROM API is not supported right now, so HW RNG and
ASLR are disabled. Also, ATF does not provide DTB, so non-secure DDR
ranges are hardcoded.
Apart from that, depending on external configuration, initial
bootloader can use two different UARTs as console: either SCIF3 or
HSCIF0. Thus, CFG_RCAR_UART is introduced.
Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
|
| H A D | platform_config.h | ab875342e1e6f7af8aa53d242296d185f456d838 Thu Feb 10 00:29:45 UTC 2022 Volodymyr Babchuk <volodymyr_babchuk@epam.com> plar: rcar: add initial support for Gen4
RCar Gen4 is the next generation of Renesas automotive
chips. Currently only RCar S4 on board Spider is available. This
platform has 8 CortexA55 cores with GICv3.
This is patch adds minimal support, so not all Gen4 features are
available. Namely, ROM API is not supported right now, so HW RNG and
ASLR are disabled. Also, ATF does not provide DTB, so non-secure DDR
ranges are hardcoded.
Apart from that, depending on external configuration, initial
bootloader can use two different UARTs as console: either SCIF3 or
HSCIF0. Thus, CFG_RCAR_UART is introduced.
Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
|
| H A D | conf.mk | ab875342e1e6f7af8aa53d242296d185f456d838 Thu Feb 10 00:29:45 UTC 2022 Volodymyr Babchuk <volodymyr_babchuk@epam.com> plar: rcar: add initial support for Gen4
RCar Gen4 is the next generation of Renesas automotive
chips. Currently only RCar S4 on board Spider is available. This
platform has 8 CortexA55 cores with GICv3.
This is patch adds minimal support, so not all Gen4 features are
available. Namely, ROM API is not supported right now, so HW RNG and
ASLR are disabled. Also, ATF does not provide DTB, so non-secure DDR
ranges are hardcoded.
Apart from that, depending on external configuration, initial
bootloader can use two different UARTs as console: either SCIF3 or
HSCIF0. Thus, CFG_RCAR_UART is introduced.
Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
|
| H A D | main.c | ab875342e1e6f7af8aa53d242296d185f456d838 Thu Feb 10 00:29:45 UTC 2022 Volodymyr Babchuk <volodymyr_babchuk@epam.com> plar: rcar: add initial support for Gen4
RCar Gen4 is the next generation of Renesas automotive
chips. Currently only RCar S4 on board Spider is available. This
platform has 8 CortexA55 cores with GICv3.
This is patch adds minimal support, so not all Gen4 features are
available. Namely, ROM API is not supported right now, so HW RNG and
ASLR are disabled. Also, ATF does not provide DTB, so non-secure DDR
ranges are hardcoded.
Apart from that, depending on external configuration, initial
bootloader can use two different UARTs as console: either SCIF3 or
HSCIF0. Thus, CFG_RCAR_UART is introduced.
Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
|