Searched hist:ab86434d690d9030cbfb0f21d7d14bdf1ca9f62e (Results 1 – 2 of 2) sorted by relevance
| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-mvebu/ |
| H A D | spi.h | ab86434d690d9030cbfb0f21d7d14bdf1ca9f62e Mon Jan 22 09:44:20 UTC 2018 Chris Packham <judge.packham@gmail.com> UPSTREAM: spi: kirkwood_spi: implement workaround for FE-9144572
Erratum NO. FE-9144572: The device SPI interface supports frequencies of
up to 50 MHz. However, due to this erratum, when the device core clock
is 250 MHz and the SPI interfaces is configured for 50MHz SPI clock and
CPOL=CPHA=1 there might occur data corruption on reads from the SPI
device.
Implement the workaround by setting the TMISO_SAMPLE value to 0x2
in the timing1 register.
Change-Id: Iee0b8cb304816d74c6442132be4cc04e6cb8adbc
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit df16881cea50a787c37591bd2168c8ea656217bd)
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| /rk3399_rockchip-uboot/drivers/spi/ |
| H A D | kirkwood_spi.c | ab86434d690d9030cbfb0f21d7d14bdf1ca9f62e Mon Jan 22 09:44:20 UTC 2018 Chris Packham <judge.packham@gmail.com> UPSTREAM: spi: kirkwood_spi: implement workaround for FE-9144572
Erratum NO. FE-9144572: The device SPI interface supports frequencies of
up to 50 MHz. However, due to this erratum, when the device core clock
is 250 MHz and the SPI interfaces is configured for 50MHz SPI clock and
CPOL=CPHA=1 there might occur data corruption on reads from the SPI
device.
Implement the workaround by setting the TMISO_SAMPLE value to 0x2
in the timing1 register.
Change-Id: Iee0b8cb304816d74c6442132be4cc04e6cb8adbc
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit df16881cea50a787c37591bd2168c8ea656217bd)
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