13e972cb9SStefan Roese /* 23e972cb9SStefan Roese * (C) Copyright 2009 33e972cb9SStefan Roese * Marvell Semiconductor <www.marvell.com> 43e972cb9SStefan Roese * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 53e972cb9SStefan Roese * 63e972cb9SStefan Roese * Derived from drivers/spi/mpc8xxx_spi.c 73e972cb9SStefan Roese * 83e972cb9SStefan Roese * SPDX-License-Identifier: GPL-2.0+ 93e972cb9SStefan Roese */ 103e972cb9SStefan Roese 113e972cb9SStefan Roese #ifndef __KW_SPI_H__ 123e972cb9SStefan Roese #define __KW_SPI_H__ 133e972cb9SStefan Roese 143e972cb9SStefan Roese /* SPI Registers on kirkwood SOC */ 153e972cb9SStefan Roese struct kwspi_registers { 163e972cb9SStefan Roese u32 ctrl; /* 0x10600 */ 173e972cb9SStefan Roese u32 cfg; /* 0x10604 */ 183e972cb9SStefan Roese u32 dout; /* 0x10608 */ 193e972cb9SStefan Roese u32 din; /* 0x1060c */ 203e972cb9SStefan Roese u32 irq_cause; /* 0x10610 */ 213e972cb9SStefan Roese u32 irq_mask; /* 0x10614 */ 2284d69191SStefan Roese u32 timing1; /* 0x10618 */ 2384d69191SStefan Roese u32 timing2; /* 0x1061c */ 2484d69191SStefan Roese u32 dw_cfg; /* 0x10620 - Direct Write Configuration */ 253e972cb9SStefan Roese }; 263e972cb9SStefan Roese 273e972cb9SStefan Roese /* They are used to define CONFIG_SYS_KW_SPI_MPP 283e972cb9SStefan Roese * each of the below #defines selects which mpp is 293e972cb9SStefan Roese * configured for each SPI signal in spi_claim_bus 303e972cb9SStefan Roese * bit 0: selects pin for MOSI (MPP1 if 0, MPP6 if 1) 313e972cb9SStefan Roese * bit 1: selects pin for SCK (MPP2 if 0, MPP10 if 1) 323e972cb9SStefan Roese * bit 2: selects pin for MISO (MPP3 if 0, MPP11 if 1) 333e972cb9SStefan Roese */ 343e972cb9SStefan Roese #define MOSI_MPP6 (1 << 0) 353e972cb9SStefan Roese #define SCK_MPP10 (1 << 1) 363e972cb9SStefan Roese #define MISO_MPP11 (1 << 2) 373e972cb9SStefan Roese 389fc56631SStefan Roese /* Control Register */ 399fc56631SStefan Roese #define KWSPI_CSN_ACT (1 << 0) /* Activates serial memory interface */ 409fc56631SStefan Roese #define KWSPI_SMEMRDY (1 << 1) /* SerMem Data xfer ready */ 419fc56631SStefan Roese #define KWSPI_CS_SHIFT 2 /* chip select shift */ 429fc56631SStefan Roese #define KWSPI_CS_MASK 0x7 /* chip select mask */ 439fc56631SStefan Roese 449fc56631SStefan Roese /* Configuration Register */ 453e972cb9SStefan Roese #define KWSPI_CLKPRESCL_MASK 0x1f 463e972cb9SStefan Roese #define KWSPI_CLKPRESCL_MIN 0x12 473e972cb9SStefan Roese #define KWSPI_XFERLEN_1BYTE 0 483e972cb9SStefan Roese #define KWSPI_XFERLEN_2BYTE (1 << 5) 493e972cb9SStefan Roese #define KWSPI_XFERLEN_MASK (1 << 5) 503e972cb9SStefan Roese #define KWSPI_ADRLEN_1BYTE 0 513e972cb9SStefan Roese #define KWSPI_ADRLEN_2BYTE (1 << 8) 523e972cb9SStefan Roese #define KWSPI_ADRLEN_3BYTE (2 << 8) 533e972cb9SStefan Roese #define KWSPI_ADRLEN_4BYTE (3 << 8) 543e972cb9SStefan Roese #define KWSPI_ADRLEN_MASK (3 << 8) 55ebfa18cbSChris Packham #define KWSPI_CPOL (1 << 11) 56ebfa18cbSChris Packham #define KWSPI_CPHA (1 << 12) 57ebfa18cbSChris Packham #define KWSPI_TXLSBF (1 << 13) 58ebfa18cbSChris Packham #define KWSPI_RXLSBF (1 << 14) 599fc56631SStefan Roese 60*ab86434dSChris Packham /* Timing Parameters 1 Register */ 61*ab86434dSChris Packham #define KW_SPI_TMISO_SAMPLE_OFFSET 6 62*ab86434dSChris Packham #define KW_SPI_TMISO_SAMPLE_MASK (0x3 << KW_SPI_TMISO_SAMPLE_OFFSET) 63*ab86434dSChris Packham #define KW_SPI_TMISO_SAMPLE_1 (1 << KW_SPI_TMISO_SAMPLE_OFFSET) 64*ab86434dSChris Packham #define KW_SPI_TMISO_SAMPLE_2 (2 << KW_SPI_TMISO_SAMPLE_OFFSET) 65*ab86434dSChris Packham 669fc56631SStefan Roese #define KWSPI_IRQUNMASK 1 /* unmask SPI interrupt */ 679fc56631SStefan Roese #define KWSPI_IRQMASK 0 /* mask SPI interrupt */ 689fc56631SStefan Roese #define KWSPI_SMEMRDIRQ 1 /* SerMem data xfer ready irq */ 699fc56631SStefan Roese 703e972cb9SStefan Roese #define KWSPI_TIMEOUT 10000 713e972cb9SStefan Roese 723e972cb9SStefan Roese #endif /* __KW_SPI_H__ */ 73