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| H A D | clk-sam9x60-pll.c | a53e4bda0e85675197f918d112546fc4e11947c9 Wed Oct 16 07:08:21 UTC 2024 Tony Han <tony.han@microchip.com> drivers: clk: sam: extend the time for waiting PLL ready
The start-up time (simulation data) of sama7g5 PLL is 50us in condition
reaching 95% of target frequency. The PLL lock status bit is not set a few
times with current timeout setting. Extend the time to make sure the check
is successful for any cases.
Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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