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/optee_os/core/drivers/clk/
H A Dclk-stm32mp13.ca32213b8169cdc33135139bd75e7a4426f3b5dd8 Fri Jan 26 12:38:07 UTC 2024 Etienne Carriere <etienne.carriere@foss.st.com> drivers: clk: fix stm32mp13 RNG1 parent clock

Correct RNG1 clock parent list as LSE is not part of according to the
STM32MP13xx reference manual.

Fixes: 5436921f6866 ("clk: stm32mp13: add all clocks for STM32MP13")
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>