Searched hist:a1d558a20f1eaeae9927abc4e0978725d33bae53 (Results 1 – 2 of 2) sorted by relevance
| /rk3399_rockchip-uboot/arch/powerpc/cpu/mpc85xx/ |
| H A D | cmd_errata.c | a1d558a20f1eaeae9927abc4e0978725d33bae53 Mon Oct 08 07:44:26 UTC 2012 York Sun <yorksun@freescale.com> powerpc/mpc85xx: Add workaround for DDR erratum A004934
After DDR controller is enabled, it performs a calibration for the
transmit data vs DQS paths. During this calibration, the DDR controller
may make an inaccurate calculation, resulting in a non-optimal tap point.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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| /rk3399_rockchip-uboot/arch/powerpc/include/asm/ |
| H A D | config_mpc85xx.h | a1d558a20f1eaeae9927abc4e0978725d33bae53 Mon Oct 08 07:44:26 UTC 2012 York Sun <yorksun@freescale.com> powerpc/mpc85xx: Add workaround for DDR erratum A004934
After DDR controller is enabled, it performs a calibration for the
transmit data vs DQS paths. During this calibration, the DDR controller
may make an inaccurate calculation, resulting in a non-optimal tap point.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|