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| H A D | phy-rockchip-naneng-combphy.c | a0d03578dd32deb6a390153c69be11fee90ef458 Mon Nov 29 03:59:58 UTC 2021 William Wu <william.wu@rock-chips.com> phy: rockchip: naneng-combphy: Adjust PLL parameters for rk3568 usb3
When do the USB 3.0 Receiver Jitter Tolerance Test on
RK3568 EVB, it fails at Sj Frequency 2.0/4.9/10.0 [MHz].
This patch adjusts the PLL parameters for USB to pass
the Receiver Jitter Tolerance Test, and it's helpful to
improve the USB 3.0 signal compatibility.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I8f9e346c5d43e8cc79767b3951b0ed82a39e1578
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