Searched hist:"9 f0ddae3175856476b3e0ce1c84bda33b87257e5" (Results 1 – 2 of 2) sorted by relevance
| /rk3399_ARM-atf/plat/xilinx/zynqmp/include/ |
| H A D | zynqmp_def.h | 9f0ddae3175856476b3e0ce1c84bda33b87257e5 Fri Mar 26 11:16:36 UTC 2021 Rajan Vaja <rajan.vaja@xilinx.com> plat: xilinx: zynqmp: Configure counter frequency during initialization
Counter frequency for generic timer of Arm-A53 based Application
Processing Unit(APU) is not configuring in case if First Stage Boot
Loader(FSBL) does not initialize counter frequency. This happens
when FSBL is running from Arm-R5 based Real-time Processing Unit(RPU).
Because of that generic timer driver functionality is not working.
So configure counter frequency during initialization.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: Icfccd59d7d2340fba25ebfb2ef6a813af4290896
|
| /rk3399_ARM-atf/plat/xilinx/zynqmp/aarch64/ |
| H A D | zynqmp_common.c | 9f0ddae3175856476b3e0ce1c84bda33b87257e5 Fri Mar 26 11:16:36 UTC 2021 Rajan Vaja <rajan.vaja@xilinx.com> plat: xilinx: zynqmp: Configure counter frequency during initialization
Counter frequency for generic timer of Arm-A53 based Application
Processing Unit(APU) is not configuring in case if First Stage Boot
Loader(FSBL) does not initialize counter frequency. This happens
when FSBL is running from Arm-R5 based Real-time Processing Unit(RPU).
Because of that generic timer driver functionality is not working.
So configure counter frequency during initialization.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: Icfccd59d7d2340fba25ebfb2ef6a813af4290896
|