Searched hist:"9 bdfc3446f8b2772b1080079f34965f4e6ee2a54" (Results 1 – 3 of 3) sorted by relevance
| /rk3399_rockchip-uboot/arch/arm/cpu/armv7/ |
| H A D | cache_v7_asm.S | 9bdfc3446f8b2772b1080079f34965f4e6ee2a54 Mon Dec 16 08:34:24 UTC 2024 Joseph Chen <chenjh@rock-chips.com> arch: arm: Add ARM_ERRATA_814220
Sync from kernel.
- ERRATA_814220:
Cache maintenance by set/way operations can execute out of order.
- Implications:
Code that intends to clean dirty data from L1 to L2 and then from L2 to L3 using
set/way operations might not behave as expected. The L2 to L3 operation might
happen first and result in dirty data remaining in L2 after the L1 to L2 operation
has completed.
If dirty data remains in L2 then an external agent, such as a DMA agent, might
observe stale data.
If the processor is reset or powered-down while dirty data remains in L2 then
the dirty data will be lost.
- Workaround:
Correct ordering between set/way cache maintenance operations can be forced by
executing a DSB before changing cache levels.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ide0a03b891cfa471f7cee2033430a02f2c5ec59b
|
| H A D | psci.S | 9bdfc3446f8b2772b1080079f34965f4e6ee2a54 Mon Dec 16 08:34:24 UTC 2024 Joseph Chen <chenjh@rock-chips.com> arch: arm: Add ARM_ERRATA_814220
Sync from kernel.
- ERRATA_814220:
Cache maintenance by set/way operations can execute out of order.
- Implications:
Code that intends to clean dirty data from L1 to L2 and then from L2 to L3 using
set/way operations might not behave as expected. The L2 to L3 operation might
happen first and result in dirty data remaining in L2 after the L1 to L2 operation
has completed.
If dirty data remains in L2 then an external agent, such as a DMA agent, might
observe stale data.
If the processor is reset or powered-down while dirty data remains in L2 then
the dirty data will be lost.
- Workaround:
Correct ordering between set/way cache maintenance operations can be forced by
executing a DSB before changing cache levels.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ide0a03b891cfa471f7cee2033430a02f2c5ec59b
|
| /rk3399_rockchip-uboot/arch/arm/ |
| H A D | Kconfig | 9bdfc3446f8b2772b1080079f34965f4e6ee2a54 Mon Dec 16 08:34:24 UTC 2024 Joseph Chen <chenjh@rock-chips.com> arch: arm: Add ARM_ERRATA_814220
Sync from kernel.
- ERRATA_814220:
Cache maintenance by set/way operations can execute out of order.
- Implications:
Code that intends to clean dirty data from L1 to L2 and then from L2 to L3 using
set/way operations might not behave as expected. The L2 to L3 operation might
happen first and result in dirty data remaining in L2 after the L1 to L2 operation
has completed.
If dirty data remains in L2 then an external agent, such as a DMA agent, might
observe stale data.
If the processor is reset or powered-down while dirty data remains in L2 then
the dirty data will be lost.
- Workaround:
Correct ordering between set/way cache maintenance operations can be forced by
executing a DSB before changing cache levels.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ide0a03b891cfa471f7cee2033430a02f2c5ec59b
|