Searched hist:"9 aea95307fdb0ffe0d3a98a17ac73e5040c9756a" (Results 1 – 3 of 3) sorted by relevance
| /rk3399_rockchip-uboot/include/ |
| H A D | e500.h | 9aea95307fdb0ffe0d3a98a17ac73e5040c9756a Sun Aug 01 23:02:45 UTC 2004 wdenk <wdenk> Patch by Jon Loeliger, 16 Jul 2004:
- support larger DDR memories up to 2G on the PC8540/8560ADS and
STXGP3 boards
- Made MPC8540/8560ADS be 33Mhz PCI by default.
- Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16
and CONFIG_L2_INIT_RAM options.
- Refactor Local Bus initialization out of SDRAM setup.
- Re-implement new version of LBC11/DDR11 errata workarounds.
- Moved board specific PCI init parts out of CPU directory.
- Added TLB entry for PCI-1 IO Memory
- Updated README.mpc85xxads
|
| /rk3399_rockchip-uboot/include/configs/ |
| H A D | MPC8540ADS.h | 9aea95307fdb0ffe0d3a98a17ac73e5040c9756a Sun Aug 01 23:02:45 UTC 2004 wdenk <wdenk> Patch by Jon Loeliger, 16 Jul 2004:
- support larger DDR memories up to 2G on the PC8540/8560ADS and
STXGP3 boards
- Made MPC8540/8560ADS be 33Mhz PCI by default.
- Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16
and CONFIG_L2_INIT_RAM options.
- Refactor Local Bus initialization out of SDRAM setup.
- Re-implement new version of LBC11/DDR11 errata workarounds.
- Moved board specific PCI init parts out of CPU directory.
- Added TLB entry for PCI-1 IO Memory
- Updated README.mpc85xxads
|
| H A D | MPC8560ADS.h | 9aea95307fdb0ffe0d3a98a17ac73e5040c9756a Sun Aug 01 23:02:45 UTC 2004 wdenk <wdenk> Patch by Jon Loeliger, 16 Jul 2004:
- support larger DDR memories up to 2G on the PC8540/8560ADS and
STXGP3 boards
- Made MPC8540/8560ADS be 33Mhz PCI by default.
- Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16
and CONFIG_L2_INIT_RAM options.
- Refactor Local Bus initialization out of SDRAM setup.
- Re-implement new version of LBC11/DDR11 errata workarounds.
- Moved board specific PCI init parts out of CPU directory.
- Added TLB entry for PCI-1 IO Memory
- Updated README.mpc85xxads
|