Searched hist:"9 a04527840dbb2c7b8bc5bd5145fa9bd26c597b4" (Results 1 – 2 of 2) sorted by relevance
| /rk3399_rockchip-uboot/drivers/pci/ |
| H A D | pci_mvebu.c | 9a04527840dbb2c7b8bc5bd5145fa9bd26c597b4 Fri Dec 25 13:41:20 UTC 2015 Phil Sutter <phil@nwl.cc> drivers/pci/pci_mvebu: Fix for boards with X4 lanes
Armada XP has support for X4 lanes, boards specify this in their
serdes_cfg. During PEX init in high_speed_env_lib.c, the configuration
is stored in GEN_PURP_RES_2_REG.
When enumerating PEX, subsequent interfaces of an X4 lane must be
skipped. Otherwise the enumeration hangs up the board.
The way this is implemented here is not exactly beautiful, but it mimics
how Marvell's BSP does it. Alternatively we could get the information
using board_serdes_cfg_get(), but that won't lead to clean code, either.
Signed-off-by: Phil Sutter <phil@nwl.cc>
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
| /rk3399_rockchip-uboot/arch/arm/mach-mvebu/include/mach/ |
| H A D | soc.h | 9a04527840dbb2c7b8bc5bd5145fa9bd26c597b4 Fri Dec 25 13:41:20 UTC 2015 Phil Sutter <phil@nwl.cc> drivers/pci/pci_mvebu: Fix for boards with X4 lanes
Armada XP has support for X4 lanes, boards specify this in their
serdes_cfg. During PEX init in high_speed_env_lib.c, the configuration
is stored in GEN_PURP_RES_2_REG.
When enumerating PEX, subsequent interfaces of an X4 lane must be
skipped. Otherwise the enumeration hangs up the board.
The way this is implemented here is not exactly beautiful, but it mimics
how Marvell's BSP does it. Alternatively we could get the information
using board_serdes_cfg_get(), but that won't lead to clean code, either.
Signed-off-by: Phil Sutter <phil@nwl.cc>
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
|