Searched hist:"99506 face112410ae37cf617b6efa809b4eee0ee" (Results 1 – 5 of 5) sorted by relevance
| /rk3399_ARM-atf/lib/extensions/trf/aarch32/ |
| H A D | trf.c | 99506face112410ae37cf617b6efa809b4eee0ee Mon Feb 13 16:38:37 UTC 2023 Boyan Karatotev <boyan.karatotev@arm.com> fix(cm): set MDCR_EL3.{NSPBE, STE} explicitly
With the introduction of FEAT_RME MDCR_EL3 bits NSPB and NSPBE depend on
each other. The enable code relies on the register being initialised to
zero and omits to reset NSPBE. However, this is not obvious. Reset the
bit explicitly to document this.
Similarly, reset the STE bit , since it's part of the feature enablement.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I3714507bae10042cdccd2b7bc713b31d4cdeb02f
|
| /rk3399_ARM-atf/lib/extensions/trf/aarch64/ |
| H A D | trf.c | 99506face112410ae37cf617b6efa809b4eee0ee Mon Feb 13 16:38:37 UTC 2023 Boyan Karatotev <boyan.karatotev@arm.com> fix(cm): set MDCR_EL3.{NSPBE, STE} explicitly
With the introduction of FEAT_RME MDCR_EL3 bits NSPB and NSPBE depend on
each other. The enable code relies on the register being initialised to
zero and omits to reset NSPBE. However, this is not obvious. Reset the
bit explicitly to document this.
Similarly, reset the STE bit , since it's part of the feature enablement.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I3714507bae10042cdccd2b7bc713b31d4cdeb02f
|
| /rk3399_ARM-atf/lib/extensions/spe/ |
| H A D | spe.c | 99506face112410ae37cf617b6efa809b4eee0ee Mon Feb 13 16:38:37 UTC 2023 Boyan Karatotev <boyan.karatotev@arm.com> fix(cm): set MDCR_EL3.{NSPBE, STE} explicitly
With the introduction of FEAT_RME MDCR_EL3 bits NSPB and NSPBE depend on
each other. The enable code relies on the register being initialised to
zero and omits to reset NSPBE. However, this is not obvious. Reset the
bit explicitly to document this.
Similarly, reset the STE bit , since it's part of the feature enablement.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I3714507bae10042cdccd2b7bc713b31d4cdeb02f
|
| /rk3399_ARM-atf/include/arch/aarch32/ |
| H A D | arch.h | 99506face112410ae37cf617b6efa809b4eee0ee Mon Feb 13 16:38:37 UTC 2023 Boyan Karatotev <boyan.karatotev@arm.com> fix(cm): set MDCR_EL3.{NSPBE, STE} explicitly
With the introduction of FEAT_RME MDCR_EL3 bits NSPB and NSPBE depend on
each other. The enable code relies on the register being initialised to
zero and omits to reset NSPBE. However, this is not obvious. Reset the
bit explicitly to document this.
Similarly, reset the STE bit , since it's part of the feature enablement.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I3714507bae10042cdccd2b7bc713b31d4cdeb02f
|
| /rk3399_ARM-atf/include/arch/aarch64/ |
| H A D | arch.h | 99506face112410ae37cf617b6efa809b4eee0ee Mon Feb 13 16:38:37 UTC 2023 Boyan Karatotev <boyan.karatotev@arm.com> fix(cm): set MDCR_EL3.{NSPBE, STE} explicitly
With the introduction of FEAT_RME MDCR_EL3 bits NSPB and NSPBE depend on
each other. The enable code relies on the register being initialised to
zero and omits to reset NSPBE. However, this is not obvious. Reset the
bit explicitly to document this.
Similarly, reset the STE bit , since it's part of the feature enablement.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I3714507bae10042cdccd2b7bc713b31d4cdeb02f
|