Searched hist:"96 ac18c9ccc77c7f57dff5651b34a3cc914c8abd" (Results 1 – 2 of 2) sorted by relevance
| /rk3399_rockchip-uboot/board/freescale/t104xrdb/ |
| H A D | ddr.h | 96ac18c9ccc77c7f57dff5651b34a3cc914c8abd Wed Feb 26 04:08:37 UTC 2014 Priyanka Jain <Priyanka.Jain@freescale.com> powerpc/t104xrdb: Update DDR initialization related settings
Update following DDR related settings for T1040RDB, T1042RDB_PI
-Correct number of chip selects to two as t1040 supports
two Chip selects.
-Update board_specific_parameters udimm structure with settings
derived via calibration.
-Update ddr_raw_timing sructure corresponding to DIMM.
-Set ODT to off. Typically on FSL board, ODT is set to 75 ohm,
but on T104xRDB, on setting this , DDR instability is observed.
Board-level debugging is in progress.
Verified the updated settings to be working fine with dual-ranked
Micron, MT18KSF51272AZ-1G6 DIMM at data rate 1600MT/s.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
|
| H A D | ddr.c | 96ac18c9ccc77c7f57dff5651b34a3cc914c8abd Wed Feb 26 04:08:37 UTC 2014 Priyanka Jain <Priyanka.Jain@freescale.com> powerpc/t104xrdb: Update DDR initialization related settings
Update following DDR related settings for T1040RDB, T1042RDB_PI
-Correct number of chip selects to two as t1040 supports
two Chip selects.
-Update board_specific_parameters udimm structure with settings
derived via calibration.
-Update ddr_raw_timing sructure corresponding to DIMM.
-Set ODT to off. Typically on FSL board, ODT is set to 75 ohm,
but on T104xRDB, on setting this , DDR instability is observed.
Board-level debugging is in progress.
Verified the updated settings to be working fine with dual-ranked
Micron, MT18KSF51272AZ-1G6 DIMM at data rate 1600MT/s.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
|