1062ef1a6SPriyanka Jain /* 2062ef1a6SPriyanka Jain * Copyright 2013 Freescale Semiconductor, Inc. 3062ef1a6SPriyanka Jain * 4062ef1a6SPriyanka Jain * SPDX-License-Identifier: GPL-2.0+ 5062ef1a6SPriyanka Jain */ 6062ef1a6SPriyanka Jain 7062ef1a6SPriyanka Jain #ifndef __DDR_H__ 8062ef1a6SPriyanka Jain #define __DDR_H__ 9062ef1a6SPriyanka Jain struct board_specific_parameters { 10062ef1a6SPriyanka Jain u32 n_ranks; 11062ef1a6SPriyanka Jain u32 datarate_mhz_high; 12062ef1a6SPriyanka Jain u32 rank_gb; 13062ef1a6SPriyanka Jain u32 clk_adjust; 14062ef1a6SPriyanka Jain u32 wrlvl_start; 15062ef1a6SPriyanka Jain u32 wrlvl_ctl_2; 16062ef1a6SPriyanka Jain u32 wrlvl_ctl_3; 17062ef1a6SPriyanka Jain }; 18062ef1a6SPriyanka Jain 19062ef1a6SPriyanka Jain /* 20062ef1a6SPriyanka Jain * These tables contain all valid speeds we want to override with board 21062ef1a6SPriyanka Jain * specific parameters. datarate_mhz_high values need to be in ascending order 22062ef1a6SPriyanka Jain * for each n_ranks group. 23062ef1a6SPriyanka Jain */ 24062ef1a6SPriyanka Jain 25062ef1a6SPriyanka Jain static const struct board_specific_parameters udimm0[] = { 26062ef1a6SPriyanka Jain /* 27062ef1a6SPriyanka Jain * memory controller 0 2896ac18c9SPriyanka Jain * num| hi| rank| clk| wrlvl | wrlvl 2996ac18c9SPriyanka Jain * ranks| mhz| GB |adjst| start | ctl2 30062ef1a6SPriyanka Jain */ 314b6067aeSPriyanka Jain #ifdef CONFIG_SYS_FSL_DDR4 32*e04f9d0cSShengzhou Liu {2, 1600, 4, 8, 6, 0x07090A0c, 0x0e0f100a}, 334b6067aeSPriyanka Jain #elif defined(CONFIG_SYS_FSL_DDR3) 34*e04f9d0cSShengzhou Liu {2, 833, 4, 8, 6, 0x06060607, 0x08080807}, 35*e04f9d0cSShengzhou Liu {2, 833, 0, 8, 6, 0x06060607, 0x08080807}, 36*e04f9d0cSShengzhou Liu {2, 1350, 4, 8, 7, 0x0708080A, 0x0A0B0C09}, 37*e04f9d0cSShengzhou Liu {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09}, 38*e04f9d0cSShengzhou Liu {2, 1666, 4, 8, 7, 0x0808090B, 0x0C0D0E0A}, 39*e04f9d0cSShengzhou Liu {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A}, 40*e04f9d0cSShengzhou Liu {1, 833, 4, 8, 6, 0x06060607, 0x08080807}, 41*e04f9d0cSShengzhou Liu {1, 833, 0, 8, 6, 0x06060607, 0x08080807}, 42*e04f9d0cSShengzhou Liu {1, 1350, 4, 8, 7, 0x0708080A, 0x0A0B0C09}, 43*e04f9d0cSShengzhou Liu {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09}, 44*e04f9d0cSShengzhou Liu {1, 1666, 4, 8, 7, 0x0808090B, 0x0C0D0E0A}, 45*e04f9d0cSShengzhou Liu {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A}, 464b6067aeSPriyanka Jain #else 474b6067aeSPriyanka Jain #error DDR type not defined 484b6067aeSPriyanka Jain #endif 49062ef1a6SPriyanka Jain {} 50062ef1a6SPriyanka Jain }; 51062ef1a6SPriyanka Jain 524b6067aeSPriyanka Jain #endif 534b6067aeSPriyanka Jain 54062ef1a6SPriyanka Jain static const struct board_specific_parameters *udimms[] = { 55062ef1a6SPriyanka Jain udimm0, 56062ef1a6SPriyanka Jain }; 57