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/rk3399_ARM-atf/plat/intel/soc/agilex/include/
H A Dagilex_clock_manager.h960a12b3fb4699cad83973c853fb5064ed6a75d0 Fri Aug 16 03:08:14 UTC 2019 Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> intel: agilex: Clear PLL lostlock bypass mode

To provide glitchless clock to downstream logic even if clock toggles

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I728d64d0ba3b4492125bea5b0737fc83180356f1
/rk3399_ARM-atf/plat/intel/soc/agilex/soc/
H A Dagilex_clock_manager.c960a12b3fb4699cad83973c853fb5064ed6a75d0 Fri Aug 16 03:08:14 UTC 2019 Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> intel: agilex: Clear PLL lostlock bypass mode

To provide glitchless clock to downstream logic even if clock toggles

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I728d64d0ba3b4492125bea5b0737fc83180356f1