Searched hist:"8 f29a74fd7a4c4ee81d60436227b04fd2ca30220" (Results 1 – 2 of 2) sorted by relevance
| /optee_os/core/arch/arm/plat-stm32mp1/ |
| H A D | main.c | 8f29a74fd7a4c4ee81d60436227b04fd2ca30220 Mon Dec 12 13:35:54 UTC 2022 Gatien Chevallier <gatien.chevallier@foss.st.com> plat-stm32mp1: enable debug feature on non secure-closed chip
Adds a new service that enables all debug features (HPD, invasive,
non invasive debug) when the chip is not in secure-closed state.
This feature is enabled when CFG_STM32_DEBUG_ACCESS is set to 'y'. It
defaults to CFG_TEE_CORE_DEBUG value.
By default, chip is secure open in order to make development and
allow debug purpose.
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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| H A D | conf.mk | 8f29a74fd7a4c4ee81d60436227b04fd2ca30220 Mon Dec 12 13:35:54 UTC 2022 Gatien Chevallier <gatien.chevallier@foss.st.com> plat-stm32mp1: enable debug feature on non secure-closed chip
Adds a new service that enables all debug features (HPD, invasive,
non invasive debug) when the chip is not in secure-closed state.
This feature is enabled when CFG_STM32_DEBUG_ACCESS is set to 'y'. It
defaults to CFG_TEE_CORE_DEBUG value.
By default, chip is secure open in order to make development and
allow debug purpose.
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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