Searched hist:"8 e1601d994e2fa8b8c7826470c3d923a684492a4" (Results 1 – 2 of 2) sorted by relevance
| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-tegra114/ |
| H A D | clock.h | 8e1601d994e2fa8b8c7826470c3d923a684492a4 Tue Sep 08 09:38:04 UTC 2015 Thierry Reding <treding@nvidia.com> ARM: tegra114: Clear IDDQ when enabling PLLC
Enabling a PLL while IDDQ is high. The Linux kernel checks for this
condition and warns about it verbosely, so while this seems to work
fine, fix it up according to the programming guidelines provided in
the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup
Sequence"). The Tegra114 TRM doesn't contain this information, but
the programming of PLLC is the same on Tegra114 and Tegra124.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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| /rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra114/ |
| H A D | clock.c | 8e1601d994e2fa8b8c7826470c3d923a684492a4 Tue Sep 08 09:38:04 UTC 2015 Thierry Reding <treding@nvidia.com> ARM: tegra114: Clear IDDQ when enabling PLLC
Enabling a PLL while IDDQ is high. The Linux kernel checks for this
condition and warns about it verbosely, so while this seems to work
fine, fix it up according to the programming guidelines provided in
the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup
Sequence"). The Tegra114 TRM doesn't contain this information, but
the programming of PLLC is the same on Tegra114 and Tegra124.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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