Searched hist:"8 ba55b28833382dcca033db78bca99f096530535" (Results 1 – 5 of 5) sorted by relevance
| /rkbin/RKBOOT/ |
| H A D | RK3588MINIALL_RAMBOOT.ini | 8ba55b28833382dcca033db78bca99f096530535 Mon Oct 24 09:06:50 UTC 2022 Tang Yun ping <typ@rock-chips.com> rk3588: ddr: update ddrbin to v1.09
build from:
a930779e06 rk3588: ddr: update ddrbin to v1.09
update feature:
1c278addf8 rk3588: ddr: lp4 support R17
1faa08ee32 rk3588: ddr: fix WRTRN_CYC_MODE bug
ef786d4bd1 rk3588: ddr: support LP5 byte mode
aff256a558 rk3588: ddr: enable LP5 DMC
0f17dc5b27 rk3588: ddr: add power_save_setting for gating some unuse clock
649abbc98b rk3588: ddr: Improve lp5 performance
cef3d77e31 rk3588: ddr: set ZQSET1TMG1.t_zq_short_interval_x1024 to 0xf0000
22f7ef4327 rk3588: ddr: boot FSP configurable by tools
7498eb52b7 rk3588: ddr: enable pstore
e2cb912b2a rk3588: ddr: clean sw*de-skew bef set rate
5be1ea1689 rk3588: ddr: adjust rk3588 LPDDR5 timing
2ccd9c35f6 rk3588: ddr: derate/per_bk_ref configurable by tools
526cc06f5b rk3588: ddr: enable lp4 lp4x cs1 ODT
149366e266 rk3588: ddr: add 256MB reg space recycle
c0cdba1f6f rk3588: ddr: LP5 WCK_ODT use 40ohm, CA ODT 80ohm
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Change-Id: I466ad2e0537313119f2f678ed3745207c498a6b3
|
| H A D | RK3588MINIALL_IPC.ini | 8ba55b28833382dcca033db78bca99f096530535 Mon Oct 24 09:06:50 UTC 2022 Tang Yun ping <typ@rock-chips.com> rk3588: ddr: update ddrbin to v1.09
build from:
a930779e06 rk3588: ddr: update ddrbin to v1.09
update feature:
1c278addf8 rk3588: ddr: lp4 support R17
1faa08ee32 rk3588: ddr: fix WRTRN_CYC_MODE bug
ef786d4bd1 rk3588: ddr: support LP5 byte mode
aff256a558 rk3588: ddr: enable LP5 DMC
0f17dc5b27 rk3588: ddr: add power_save_setting for gating some unuse clock
649abbc98b rk3588: ddr: Improve lp5 performance
cef3d77e31 rk3588: ddr: set ZQSET1TMG1.t_zq_short_interval_x1024 to 0xf0000
22f7ef4327 rk3588: ddr: boot FSP configurable by tools
7498eb52b7 rk3588: ddr: enable pstore
e2cb912b2a rk3588: ddr: clean sw*de-skew bef set rate
5be1ea1689 rk3588: ddr: adjust rk3588 LPDDR5 timing
2ccd9c35f6 rk3588: ddr: derate/per_bk_ref configurable by tools
526cc06f5b rk3588: ddr: enable lp4 lp4x cs1 ODT
149366e266 rk3588: ddr: add 256MB reg space recycle
c0cdba1f6f rk3588: ddr: LP5 WCK_ODT use 40ohm, CA ODT 80ohm
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Change-Id: I466ad2e0537313119f2f678ed3745207c498a6b3
|
| H A D | RK3588MINIALL.ini | 8ba55b28833382dcca033db78bca99f096530535 Mon Oct 24 09:06:50 UTC 2022 Tang Yun ping <typ@rock-chips.com> rk3588: ddr: update ddrbin to v1.09
build from:
a930779e06 rk3588: ddr: update ddrbin to v1.09
update feature:
1c278addf8 rk3588: ddr: lp4 support R17
1faa08ee32 rk3588: ddr: fix WRTRN_CYC_MODE bug
ef786d4bd1 rk3588: ddr: support LP5 byte mode
aff256a558 rk3588: ddr: enable LP5 DMC
0f17dc5b27 rk3588: ddr: add power_save_setting for gating some unuse clock
649abbc98b rk3588: ddr: Improve lp5 performance
cef3d77e31 rk3588: ddr: set ZQSET1TMG1.t_zq_short_interval_x1024 to 0xf0000
22f7ef4327 rk3588: ddr: boot FSP configurable by tools
7498eb52b7 rk3588: ddr: enable pstore
e2cb912b2a rk3588: ddr: clean sw*de-skew bef set rate
5be1ea1689 rk3588: ddr: adjust rk3588 LPDDR5 timing
2ccd9c35f6 rk3588: ddr: derate/per_bk_ref configurable by tools
526cc06f5b rk3588: ddr: enable lp4 lp4x cs1 ODT
149366e266 rk3588: ddr: add 256MB reg space recycle
c0cdba1f6f rk3588: ddr: LP5 WCK_ODT use 40ohm, CA ODT 80ohm
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Change-Id: I466ad2e0537313119f2f678ed3745207c498a6b3
|
| /rkbin/doc/release/ |
| H A D | RK3588_CN.md | 8ba55b28833382dcca033db78bca99f096530535 Mon Oct 24 09:06:50 UTC 2022 Tang Yun ping <typ@rock-chips.com> rk3588: ddr: update ddrbin to v1.09
build from:
a930779e06 rk3588: ddr: update ddrbin to v1.09
update feature:
1c278addf8 rk3588: ddr: lp4 support R17
1faa08ee32 rk3588: ddr: fix WRTRN_CYC_MODE bug
ef786d4bd1 rk3588: ddr: support LP5 byte mode
aff256a558 rk3588: ddr: enable LP5 DMC
0f17dc5b27 rk3588: ddr: add power_save_setting for gating some unuse clock
649abbc98b rk3588: ddr: Improve lp5 performance
cef3d77e31 rk3588: ddr: set ZQSET1TMG1.t_zq_short_interval_x1024 to 0xf0000
22f7ef4327 rk3588: ddr: boot FSP configurable by tools
7498eb52b7 rk3588: ddr: enable pstore
e2cb912b2a rk3588: ddr: clean sw*de-skew bef set rate
5be1ea1689 rk3588: ddr: adjust rk3588 LPDDR5 timing
2ccd9c35f6 rk3588: ddr: derate/per_bk_ref configurable by tools
526cc06f5b rk3588: ddr: enable lp4 lp4x cs1 ODT
149366e266 rk3588: ddr: add 256MB reg space recycle
c0cdba1f6f rk3588: ddr: LP5 WCK_ODT use 40ohm, CA ODT 80ohm
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Change-Id: I466ad2e0537313119f2f678ed3745207c498a6b3
|
| H A D | RK3588_EN.md | 8ba55b28833382dcca033db78bca99f096530535 Mon Oct 24 09:06:50 UTC 2022 Tang Yun ping <typ@rock-chips.com> rk3588: ddr: update ddrbin to v1.09
build from:
a930779e06 rk3588: ddr: update ddrbin to v1.09
update feature:
1c278addf8 rk3588: ddr: lp4 support R17
1faa08ee32 rk3588: ddr: fix WRTRN_CYC_MODE bug
ef786d4bd1 rk3588: ddr: support LP5 byte mode
aff256a558 rk3588: ddr: enable LP5 DMC
0f17dc5b27 rk3588: ddr: add power_save_setting for gating some unuse clock
649abbc98b rk3588: ddr: Improve lp5 performance
cef3d77e31 rk3588: ddr: set ZQSET1TMG1.t_zq_short_interval_x1024 to 0xf0000
22f7ef4327 rk3588: ddr: boot FSP configurable by tools
7498eb52b7 rk3588: ddr: enable pstore
e2cb912b2a rk3588: ddr: clean sw*de-skew bef set rate
5be1ea1689 rk3588: ddr: adjust rk3588 LPDDR5 timing
2ccd9c35f6 rk3588: ddr: derate/per_bk_ref configurable by tools
526cc06f5b rk3588: ddr: enable lp4 lp4x cs1 ODT
149366e266 rk3588: ddr: add 256MB reg space recycle
c0cdba1f6f rk3588: ddr: LP5 WCK_ODT use 40ohm, CA ODT 80ohm
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Change-Id: I466ad2e0537313119f2f678ed3745207c498a6b3
|