Searched hist:"89 a54abf1bd1a8a9ebbea9808199ec8ee3d902bd" (Results 1 – 4 of 4) sorted by relevance
| /rk3399_rockchip-uboot/arch/arm/mach-socfpga/ |
| H A D | wrap_sdram_config.c | 89a54abf1bd1a8a9ebbea9808199ec8ee3d902bd Wed Sep 21 02:25:56 UTC 2016 Chin Liang See <clsee@altera.com> ddr: altera: Configuring SDRAM extra cycles timing parameters
To enable configuration of sdr.ctrlcfg.extratime1 register which enable
extra clocks for read to write command timing. This is critical to
ensure successful LPDDR2 interface
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
|
| H A D | qts-filter.sh | 89a54abf1bd1a8a9ebbea9808199ec8ee3d902bd Wed Sep 21 02:25:56 UTC 2016 Chin Liang See <clsee@altera.com> ddr: altera: Configuring SDRAM extra cycles timing parameters
To enable configuration of sdr.ctrlcfg.extratime1 register which enable
extra clocks for read to write command timing. This is critical to
ensure successful LPDDR2 interface
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
|
| /rk3399_rockchip-uboot/arch/arm/mach-socfpga/include/mach/ |
| H A D | sdram.h | 89a54abf1bd1a8a9ebbea9808199ec8ee3d902bd Wed Sep 21 02:25:56 UTC 2016 Chin Liang See <clsee@altera.com> ddr: altera: Configuring SDRAM extra cycles timing parameters
To enable configuration of sdr.ctrlcfg.extratime1 register which enable
extra clocks for read to write command timing. This is critical to
ensure successful LPDDR2 interface
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
|
| /rk3399_rockchip-uboot/drivers/ddr/altera/ |
| H A D | sdram.c | 89a54abf1bd1a8a9ebbea9808199ec8ee3d902bd Wed Sep 21 02:25:56 UTC 2016 Chin Liang See <clsee@altera.com> ddr: altera: Configuring SDRAM extra cycles timing parameters
To enable configuration of sdr.ctrlcfg.extratime1 register which enable
extra clocks for read to write command timing. This is critical to
ensure successful LPDDR2 interface
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
|