Searched hist:"8975 f317e7608c832192b71531901602dc625484" (Results 1 – 3 of 3) sorted by relevance
| /rk3399_ARM-atf/plat/xilinx/zynqmp/pm_service/ |
| H A D | pm_api_clock.h | 8975f317e7608c832192b71531901602dc625484 Wed Jan 02 20:46:46 UTC 2019 Jolly Shah <jollys@xilinx.com> zynqmp: pm: Buffer the PLL mode that is set using IOCTL API
When linux calls pm_ioctl_set_pll_frac_mode() it doesn't expect the
fractional mode to be changed in hardware. Furthermore, even before this
patch setting the mode which is done by writing into register takes
no effect until the PLL reset is deasserted, i.e. until linux "enables"
the PLL. To adjust the code to system-level PLL EEMI API and avoid
unnecessary IPIs that would otherwise be issued, we buffer the mode
value set via IOCTL until the PLL mode really needs to be set.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
|
| H A D | pm_api_ioctl.c | 8975f317e7608c832192b71531901602dc625484 Wed Jan 02 20:46:46 UTC 2019 Jolly Shah <jollys@xilinx.com> zynqmp: pm: Buffer the PLL mode that is set using IOCTL API
When linux calls pm_ioctl_set_pll_frac_mode() it doesn't expect the
fractional mode to be changed in hardware. Furthermore, even before this
patch setting the mode which is done by writing into register takes
no effect until the PLL reset is deasserted, i.e. until linux "enables"
the PLL. To adjust the code to system-level PLL EEMI API and avoid
unnecessary IPIs that would otherwise be issued, we buffer the mode
value set via IOCTL until the PLL mode really needs to be set.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
|
| H A D | pm_api_clock.c | 8975f317e7608c832192b71531901602dc625484 Wed Jan 02 20:46:46 UTC 2019 Jolly Shah <jollys@xilinx.com> zynqmp: pm: Buffer the PLL mode that is set using IOCTL API
When linux calls pm_ioctl_set_pll_frac_mode() it doesn't expect the
fractional mode to be changed in hardware. Furthermore, even before this
patch setting the mode which is done by writing into register takes
no effect until the PLL reset is deasserted, i.e. until linux "enables"
the PLL. To adjust the code to system-level PLL EEMI API and avoid
unnecessary IPIs that would otherwise be issued, we buffer the mode
value set via IOCTL until the PLL mode really needs to be set.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
|