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| /rk3399_ARM-atf/docs/design/ |
| H A D | cpu-specific-build-macros.rst | 83e955241aafb4bfac8f2b6db402d7bfc34a5167 Wed Dec 18 21:56:27 UTC 2019 Madhukar Pappireddy <madhukar.pappireddy@arm.com> Workaround for Hercules erratum 1688305
Erratum 1688305 is a Cat B erratum present in r0p0, r0p1 versions
of Hercules core. The erratum can be avoided by setting bit 1 of the
implementation defined register CPUACTLR2_EL1 to 1 to prevent store-
release from being dispatched before it is the oldest.
Change-Id: I2ac04f5d9423868b6cdd4ceb3d0ffa46e570efed
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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| /rk3399_ARM-atf/lib/cpus/ |
| H A D | cpu-ops.mk | 83e955241aafb4bfac8f2b6db402d7bfc34a5167 Wed Dec 18 21:56:27 UTC 2019 Madhukar Pappireddy <madhukar.pappireddy@arm.com> Workaround for Hercules erratum 1688305
Erratum 1688305 is a Cat B erratum present in r0p0, r0p1 versions
of Hercules core. The erratum can be avoided by setting bit 1 of the
implementation defined register CPUACTLR2_EL1 to 1 to prevent store-
release from being dispatched before it is the oldest.
Change-Id: I2ac04f5d9423868b6cdd4ceb3d0ffa46e570efed
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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