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| H A D | emif.h | 802bb57a584db2202a47d41ac730fe76ddeb4f33 Mon Feb 16 04:45:56 UTC 2015 Lokesh Vutla <lokeshvutla@ti.com> ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value
The value in SDRAM_REF_CTRL controls the delay time between
the initial rising edge of DDR_RESETn to rising edge of DDR_CKE
(JEDEC specs this as 500us). In order to achieve this, SDRAM_REF_CTRL
should be written with a value corresponding to 500us delay before
starting DDR initialization sequence, and configure proper
value at the end of sequence.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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