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/rk3399_rockchip-uboot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dlowlevel.S7cfbb4abe3c4755363aa3d692511bf187852adf6 Thu Nov 17 06:59:53 UTC 2016 Priyanka Jain <priyanka.jain@nxp.com> armv8: fsl-layerscape: Update TZASC registers type

TZASC registers like TZASC_GATE_KEEPER, TZASC_REGION_ATTRIBUTES
are 32-bit regsiters.
So while doing register load-store operations, 32-bit intermediate
register, w0 should be used.
Update x0 register to w0 register type.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>