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| /rk3399_rockchip-uboot/drivers/clk/rockchip/ |
| H A D | clk_rk3308.c | 7b1c1c4be3bdc441501dcfbfa08d53b38e777147 Thu Jun 07 03:34:32 UTC 2018 Finley Xiao <finley.xiao@rock-chips.com> clk: rockchip: rk3308: check pll rate before set and get rate
As clk_set_defaults() is called before rk3308_clk_probe() and pll rate are
assigned when clk probe at present, so if enable kernel dtb and it contains
"assigned-clocks" property, the pll rate will be zero when set and get clk rate.
In order to fix this, check and assign pll rate before set and get rate.
Change-Id: Ic8e9fcf487e7531a8ef23f54d0786e0cbc9a9f4a
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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