Searched hist:"79 cf644e2d330cf6fdd3ef489e44f9fb1c6f196a" (Results 1 – 2 of 2) sorted by relevance
| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-tegra124/ |
| H A D | mc.h | 79cf644e2d330cf6fdd3ef489e44f9fb1c6f196a Tue Apr 21 05:18:38 UTC 2015 Thierry Reding <treding@nvidia.com> ARM: tegra: Enable SMMU when going non-secure
Make sure to enable the SMMU when booting the kernel in non-secure mode.
This is necessary because some of the SMMU registers are restricted to
TrustZone-secured requestors, hence the kernel wouldn't be able to turn
the SMMU on. At the same time, enable translation for all memory clients
for the same reasons. The kernel will still be able to control SMMU IOVA
translation using the per-SWGROUP enable bits.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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| /rk3399_rockchip-uboot/arch/arm/mach-tegra/ |
| H A D | ap.c | 79cf644e2d330cf6fdd3ef489e44f9fb1c6f196a Tue Apr 21 05:18:38 UTC 2015 Thierry Reding <treding@nvidia.com> ARM: tegra: Enable SMMU when going non-secure
Make sure to enable the SMMU when booting the kernel in non-secure mode.
This is necessary because some of the SMMU registers are restricted to
TrustZone-secured requestors, hence the kernel wouldn't be able to turn
the SMMU on. At the same time, enable translation for all memory clients
for the same reasons. The kernel will still be able to control SMMU IOVA
translation using the per-SWGROUP enable bits.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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