1df3443dfSBryan Wu /* 2df3443dfSBryan Wu * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 3df3443dfSBryan Wu * 4*5b8031ccSTom Rini * SPDX-License-Identifier: GPL-2.0 5df3443dfSBryan Wu */ 6df3443dfSBryan Wu 7df3443dfSBryan Wu #ifndef _TEGRA124_MC_H_ 8df3443dfSBryan Wu #define _TEGRA124_MC_H_ 9df3443dfSBryan Wu 10df3443dfSBryan Wu /** 11df3443dfSBryan Wu * Defines the memory controller registers we need/care about 12df3443dfSBryan Wu */ 13df3443dfSBryan Wu struct mc_ctlr { 14df3443dfSBryan Wu u32 reserved0[4]; /* offset 0x00 - 0x0C */ 15df3443dfSBryan Wu u32 mc_smmu_config; /* offset 0x10 */ 16df3443dfSBryan Wu u32 mc_smmu_tlb_config; /* offset 0x14 */ 17df3443dfSBryan Wu u32 mc_smmu_ptc_config; /* offset 0x18 */ 18df3443dfSBryan Wu u32 mc_smmu_ptb_asid; /* offset 0x1C */ 19df3443dfSBryan Wu u32 mc_smmu_ptb_data; /* offset 0x20 */ 20df3443dfSBryan Wu u32 reserved1[3]; /* offset 0x24 - 0x2C */ 21df3443dfSBryan Wu u32 mc_smmu_tlb_flush; /* offset 0x30 */ 22df3443dfSBryan Wu u32 mc_smmu_ptc_flush; /* offset 0x34 */ 23df3443dfSBryan Wu u32 reserved2[6]; /* offset 0x38 - 0x4C */ 24df3443dfSBryan Wu u32 mc_emem_cfg; /* offset 0x50 */ 25df3443dfSBryan Wu u32 mc_emem_adr_cfg; /* offset 0x54 */ 26df3443dfSBryan Wu u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */ 27df3443dfSBryan Wu u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */ 28bfb2c8d3SIan Campbell u32 reserved3[4]; /* offset 0x60 - 0x6C */ 29bfb2c8d3SIan Campbell u32 mc_security_cfg0; /* offset 0x70 */ 30bfb2c8d3SIan Campbell u32 mc_security_cfg1; /* offset 0x74 */ 31bfb2c8d3SIan Campbell u32 reserved4[6]; /* offset 0x7C - 0x8C */ 32df3443dfSBryan Wu u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */ 33bfb2c8d3SIan Campbell u32 reserved5[74]; /* offset 0x100 - 0x224 */ 34bfb2c8d3SIan Campbell u32 mc_smmu_translation_enable_0; /* offset 0x228 */ 35bfb2c8d3SIan Campbell u32 mc_smmu_translation_enable_1; /* offset 0x22C */ 36bfb2c8d3SIan Campbell u32 mc_smmu_translation_enable_2; /* offset 0x230 */ 37bfb2c8d3SIan Campbell u32 mc_smmu_translation_enable_3; /* offset 0x234 */ 38bfb2c8d3SIan Campbell u32 mc_smmu_afi_asid; /* offset 0x238 */ 39bfb2c8d3SIan Campbell u32 mc_smmu_avpc_asid; /* offset 0x23C */ 40bfb2c8d3SIan Campbell u32 mc_smmu_dc_asid; /* offset 0x240 */ 41bfb2c8d3SIan Campbell u32 mc_smmu_dcb_asid; /* offset 0x244 */ 42bfb2c8d3SIan Campbell u32 reserved6[2]; /* offset 0x248 - 0x24C */ 43bfb2c8d3SIan Campbell u32 mc_smmu_hc_asid; /* offset 0x250 */ 44bfb2c8d3SIan Campbell u32 mc_smmu_hda_asid; /* offset 0x254 */ 45bfb2c8d3SIan Campbell u32 mc_smmu_isp2_asid; /* offset 0x258 */ 46bfb2c8d3SIan Campbell u32 reserved7[2]; /* offset 0x25C - 0x260 */ 47bfb2c8d3SIan Campbell u32 mc_smmu_msenc_asid; /* offset 0x264 */ 48bfb2c8d3SIan Campbell u32 mc_smmu_nv_asid; /* offset 0x268 */ 49bfb2c8d3SIan Campbell u32 mc_smmu_nv2_asid; /* offset 0x26C */ 50bfb2c8d3SIan Campbell u32 mc_smmu_ppcs_asid; /* offset 0x270 */ 51bfb2c8d3SIan Campbell u32 mc_smmu_sata_asid; /* offset 0x274 */ 52bfb2c8d3SIan Campbell u32 reserved8[1]; /* offset 0x278 */ 53bfb2c8d3SIan Campbell u32 mc_smmu_vde_asid; /* offset 0x27C */ 54bfb2c8d3SIan Campbell u32 mc_smmu_vi_asid; /* offset 0x280 */ 55bfb2c8d3SIan Campbell u32 mc_smmu_vic_asid; /* offset 0x284 */ 56bfb2c8d3SIan Campbell u32 mc_smmu_xusb_host_asid; /* offset 0x288 */ 57bfb2c8d3SIan Campbell u32 mc_smmu_xusb_dev_asid; /* offset 0x28C */ 58bfb2c8d3SIan Campbell u32 reserved9[1]; /* offset 0x290 */ 59bfb2c8d3SIan Campbell u32 mc_smmu_tsec_asid; /* offset 0x294 */ 60bfb2c8d3SIan Campbell u32 mc_smmu_ppcs1_asid; /* offset 0x298 */ 61bfb2c8d3SIan Campbell u32 reserved10[235]; /* offset 0x29C - 0x644 */ 62df3443dfSBryan Wu u32 mc_video_protect_bom; /* offset 0x648 */ 63df3443dfSBryan Wu u32 mc_video_protect_size_mb; /* offset 0x64c */ 64df3443dfSBryan Wu u32 mc_video_protect_reg_ctrl; /* offset 0x650 */ 65df3443dfSBryan Wu }; 66df3443dfSBryan Wu 6779cf644eSThierry Reding #define TEGRA_MC_SMMU_CONFIG_ENABLE (1 << 0) 6879cf644eSThierry Reding 69df3443dfSBryan Wu #define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED (0 << 0) 70df3443dfSBryan Wu #define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED (1 << 0) 71df3443dfSBryan Wu 72df3443dfSBryan Wu #endif /* _TEGRA124_MC_H_ */ 73