Searched hist:"73 ba32eb0f6cbb6ebbc59f13ea7eee44b387fe48" (Results 1 – 4 of 4) sorted by relevance
| /optee_os/core/drivers/crypto/se050/glue/ |
| H A D | i2c_stm32.c | 73ba32eb0f6cbb6ebbc59f13ea7eee44b387fe48 Tue May 23 10:00:08 UTC 2023 Etienne Carriere <etienne.carriere@foss.st.com> drivers: stm32_i2c: support CFG_DRIVERS_PINCTRL
Updates stm32_i2c driver for when CFG_DRIVERS_PINCTRL is enabled making
I2C driver to get pin control configuration using the generic pin
control framework. When enabled, stm32_i2c driver get the active and
sleep pin control configuration from the device tree. Sleep pinctrl
configuration is optional.
SE050 and STM32MP1 PMIC drivers that use the stm32_i2c bus are both
updated accordingly.
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
|
| /optee_os/core/include/drivers/ |
| H A D | stm32_i2c.h | 73ba32eb0f6cbb6ebbc59f13ea7eee44b387fe48 Tue May 23 10:00:08 UTC 2023 Etienne Carriere <etienne.carriere@foss.st.com> drivers: stm32_i2c: support CFG_DRIVERS_PINCTRL
Updates stm32_i2c driver for when CFG_DRIVERS_PINCTRL is enabled making
I2C driver to get pin control configuration using the generic pin
control framework. When enabled, stm32_i2c driver get the active and
sleep pin control configuration from the device tree. Sleep pinctrl
configuration is optional.
SE050 and STM32MP1 PMIC drivers that use the stm32_i2c bus are both
updated accordingly.
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
|
| /optee_os/core/arch/arm/plat-stm32mp1/drivers/ |
| H A D | stm32mp1_pmic.c | 73ba32eb0f6cbb6ebbc59f13ea7eee44b387fe48 Tue May 23 10:00:08 UTC 2023 Etienne Carriere <etienne.carriere@foss.st.com> drivers: stm32_i2c: support CFG_DRIVERS_PINCTRL
Updates stm32_i2c driver for when CFG_DRIVERS_PINCTRL is enabled making
I2C driver to get pin control configuration using the generic pin
control framework. When enabled, stm32_i2c driver get the active and
sleep pin control configuration from the device tree. Sleep pinctrl
configuration is optional.
SE050 and STM32MP1 PMIC drivers that use the stm32_i2c bus are both
updated accordingly.
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
|
| /optee_os/core/drivers/ |
| H A D | stm32_i2c.c | 73ba32eb0f6cbb6ebbc59f13ea7eee44b387fe48 Tue May 23 10:00:08 UTC 2023 Etienne Carriere <etienne.carriere@foss.st.com> drivers: stm32_i2c: support CFG_DRIVERS_PINCTRL
Updates stm32_i2c driver for when CFG_DRIVERS_PINCTRL is enabled making
I2C driver to get pin control configuration using the generic pin
control framework. When enabled, stm32_i2c driver get the active and
sleep pin control configuration from the device tree. Sleep pinctrl
configuration is optional.
SE050 and STM32MP1 PMIC drivers that use the stm32_i2c bus are both
updated accordingly.
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
|