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| H A D | spi-nor-ids.c | 736113f20e9126a8387b5ffaba5f4086a27fd27d Fri Oct 11 07:58:19 UTC 2019 Vignesh Raghavendra <vigneshr@ti.com> UPSTREAM: spi-nor: spi-nor-ids: Add entries for mt25q variants
mt25q* flashes support stateless 4 byte addressing opcodes. Add entries
for the same. These flashes have bit 6 set in 5th byte of READ ID
response when compared to n25q* variants.
Change-Id: I1cd2c371bb97a255cdeafaf4d18eec24dd8b9f2f
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 8651593a8ce0c0599c993d76d2a927b125175cef)
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