Searched hist:"6 d2b9da19cbfe0b7da7e9ae0bf2a1a000f2e2804" (Results 1 – 5 of 5) sorted by relevance
| /rk3399_rockchip-uboot/arch/powerpc/cpu/mpc85xx/ |
| H A D | release.S | 6d2b9da19cbfe0b7da7e9ae0bf2a1a000f2e2804 Mon Oct 08 07:44:08 UTC 2012 York Sun <yorksun@freescale.com> powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500
Using E6500 L1 cache as initram requires L2 cache enabled.
Add l2-cache cluster enabling.
Setup stash id for L1 cache as (coreID) * 2 + 32 + 0
Setup stash id for L2 cache as (cluster) * 2 + 32 + 1
Stash id for L2 is only set for Chassis 2.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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| H A D | fdt.c | 6d2b9da19cbfe0b7da7e9ae0bf2a1a000f2e2804 Mon Oct 08 07:44:08 UTC 2012 York Sun <yorksun@freescale.com> powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500
Using E6500 L1 cache as initram requires L2 cache enabled.
Add l2-cache cluster enabling.
Setup stash id for L1 cache as (coreID) * 2 + 32 + 0
Setup stash id for L2 cache as (cluster) * 2 + 32 + 1
Stash id for L2 is only set for Chassis 2.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
| H A D | start.S | 6d2b9da19cbfe0b7da7e9ae0bf2a1a000f2e2804 Mon Oct 08 07:44:08 UTC 2012 York Sun <yorksun@freescale.com> powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500
Using E6500 L1 cache as initram requires L2 cache enabled.
Add l2-cache cluster enabling.
Setup stash id for L1 cache as (coreID) * 2 + 32 + 0
Setup stash id for L2 cache as (cluster) * 2 + 32 + 1
Stash id for L2 is only set for Chassis 2.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
| H A D | cpu_init.c | 6d2b9da19cbfe0b7da7e9ae0bf2a1a000f2e2804 Mon Oct 08 07:44:08 UTC 2012 York Sun <yorksun@freescale.com> powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500
Using E6500 L1 cache as initram requires L2 cache enabled.
Add l2-cache cluster enabling.
Setup stash id for L1 cache as (coreID) * 2 + 32 + 0
Setup stash id for L2 cache as (cluster) * 2 + 32 + 1
Stash id for L2 is only set for Chassis 2.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
| /rk3399_rockchip-uboot/arch/powerpc/include/asm/ |
| H A D | immap_85xx.h | 6d2b9da19cbfe0b7da7e9ae0bf2a1a000f2e2804 Mon Oct 08 07:44:08 UTC 2012 York Sun <yorksun@freescale.com> powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500
Using E6500 L1 cache as initram requires L2 cache enabled.
Add l2-cache cluster enabling.
Setup stash id for L1 cache as (coreID) * 2 + 32 + 0
Setup stash id for L2 cache as (cluster) * 2 + 32 + 1
Stash id for L2 is only set for Chassis 2.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|