Home
last modified time | relevance | path

Searched hist:"6 b50f62cc4df7e2961fb45980cf91bb424ee263b" (Results 1 – 1 of 1) sorted by relevance

/rk3399_rockchip-uboot/board/freescale/b4860qds/
H A Db4_pbi.cfg6b50f62cc4df7e2961fb45980cf91bb424ee263b Sat Mar 08 11:15:04 UTC 2014 Prabhakar Kushwaha <prabhakar@freescale.com> board/b4860qds:Slow MDC clock to comply IEEE specs in PBI config

The MDC generate by default value of MDIO_CLK_DIV is too high i.e. higher
than 2.5 MHZ. It violates the IEEE specs.

So Slow MDC clock to comply IEEE specs

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>