| /rk3399_ARM-atf/plat/mediatek/drivers/disp/ |
| H A D | rules.mk | 69970765fa9f9ec7a9de2408e50ea21d681df1c2 Mon Jul 07 06:06:57 UTC 2025 xiandong.wang <xiandong.wang@mediatek.corp-partner.google.com> feat(mt8189): add support display driver
After a suspend/resume cycle, the display's register state reverts to
its default state. Therefore, display must set the register state
to normal, allowing the GCE and CPU to have the authority to configure
this register.
Signed-off-by: xiandong.wang <xiandong.wang@mediatek.com>
Change-Id: I124eb0eae17d7ab263c23374b70c3b6155dc7c3a
|
| H A D | mtk_disp_priv.h | 69970765fa9f9ec7a9de2408e50ea21d681df1c2 Mon Jul 07 06:06:57 UTC 2025 xiandong.wang <xiandong.wang@mediatek.corp-partner.google.com> feat(mt8189): add support display driver
After a suspend/resume cycle, the display's register state reverts to
its default state. Therefore, display must set the register state
to normal, allowing the GCE and CPU to have the authority to configure
this register.
Signed-off-by: xiandong.wang <xiandong.wang@mediatek.com>
Change-Id: I124eb0eae17d7ab263c23374b70c3b6155dc7c3a
|
| H A D | mtk_disp_smc.c | 69970765fa9f9ec7a9de2408e50ea21d681df1c2 Mon Jul 07 06:06:57 UTC 2025 xiandong.wang <xiandong.wang@mediatek.corp-partner.google.com> feat(mt8189): add support display driver
After a suspend/resume cycle, the display's register state reverts to
its default state. Therefore, display must set the register state
to normal, allowing the GCE and CPU to have the authority to configure
this register.
Signed-off-by: xiandong.wang <xiandong.wang@mediatek.com>
Change-Id: I124eb0eae17d7ab263c23374b70c3b6155dc7c3a
|
| /rk3399_ARM-atf/plat/mediatek/drivers/disp/mt8189/ |
| H A D | mtk_disp_plat.c | 69970765fa9f9ec7a9de2408e50ea21d681df1c2 Mon Jul 07 06:06:57 UTC 2025 xiandong.wang <xiandong.wang@mediatek.corp-partner.google.com> feat(mt8189): add support display driver
After a suspend/resume cycle, the display's register state reverts to
its default state. Therefore, display must set the register state
to normal, allowing the GCE and CPU to have the authority to configure
this register.
Signed-off-by: xiandong.wang <xiandong.wang@mediatek.com>
Change-Id: I124eb0eae17d7ab263c23374b70c3b6155dc7c3a
|
| /rk3399_ARM-atf/plat/mediatek/mt8189/include/ |
| H A D | platform_def.h | 69970765fa9f9ec7a9de2408e50ea21d681df1c2 Mon Jul 07 06:06:57 UTC 2025 xiandong.wang <xiandong.wang@mediatek.corp-partner.google.com> feat(mt8189): add support display driver
After a suspend/resume cycle, the display's register state reverts to
its default state. Therefore, display must set the register state
to normal, allowing the GCE and CPU to have the authority to configure
this register.
Signed-off-by: xiandong.wang <xiandong.wang@mediatek.com>
Change-Id: I124eb0eae17d7ab263c23374b70c3b6155dc7c3a
|
| /rk3399_ARM-atf/plat/mediatek/include/ |
| H A D | mtk_sip_def.h | 69970765fa9f9ec7a9de2408e50ea21d681df1c2 Mon Jul 07 06:06:57 UTC 2025 xiandong.wang <xiandong.wang@mediatek.corp-partner.google.com> feat(mt8189): add support display driver
After a suspend/resume cycle, the display's register state reverts to
its default state. Therefore, display must set the register state
to normal, allowing the GCE and CPU to have the authority to configure
this register.
Signed-off-by: xiandong.wang <xiandong.wang@mediatek.com>
Change-Id: I124eb0eae17d7ab263c23374b70c3b6155dc7c3a
|
| /rk3399_ARM-atf/plat/mediatek/mt8189/ |
| H A D | platform.mk | 69970765fa9f9ec7a9de2408e50ea21d681df1c2 Mon Jul 07 06:06:57 UTC 2025 xiandong.wang <xiandong.wang@mediatek.corp-partner.google.com> feat(mt8189): add support display driver
After a suspend/resume cycle, the display's register state reverts to
its default state. Therefore, display must set the register state
to normal, allowing the GCE and CPU to have the authority to configure
this register.
Signed-off-by: xiandong.wang <xiandong.wang@mediatek.com>
Change-Id: I124eb0eae17d7ab263c23374b70c3b6155dc7c3a
|