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/optee_os/core/arch/arm/plat-stm32mp1/drivers/
H A Dstm32mp1_pwr.c68c4a16b37c797cf2a3d49af419f238e23cc8e4c Wed May 15 09:24:25 UTC 2019 Etienne Carriere <etienne.carriere@st.com> stm32mp1: use phys_to_virt_io_secure() where expected

This change updates platforms and drivers to use io_pa_or_va_secure()
when expecting a secure mapped address.

PWR, RCC, GIC, TAMP, BSEC, ETZPC, I2C are always secure (when embedded).

RNG uses a secure or non-secure mapping according to its registration in
platform shared_resource driver.

GPIOs IO memory is always access though non-secure mapped virtual
addresses.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
/optee_os/core/drivers/
H A Dstm32_i2c.c68c4a16b37c797cf2a3d49af419f238e23cc8e4c Wed May 15 09:24:25 UTC 2019 Etienne Carriere <etienne.carriere@st.com> stm32mp1: use phys_to_virt_io_secure() where expected

This change updates platforms and drivers to use io_pa_or_va_secure()
when expecting a secure mapped address.

PWR, RCC, GIC, TAMP, BSEC, ETZPC, I2C are always secure (when embedded).

RNG uses a secure or non-secure mapping according to its registration in
platform shared_resource driver.

GPIOs IO memory is always access though non-secure mapped virtual
addresses.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
H A Dstm32_bsec.c68c4a16b37c797cf2a3d49af419f238e23cc8e4c Wed May 15 09:24:25 UTC 2019 Etienne Carriere <etienne.carriere@st.com> stm32mp1: use phys_to_virt_io_secure() where expected

This change updates platforms and drivers to use io_pa_or_va_secure()
when expecting a secure mapped address.

PWR, RCC, GIC, TAMP, BSEC, ETZPC, I2C are always secure (when embedded).

RNG uses a secure or non-secure mapping according to its registration in
platform shared_resource driver.

GPIOs IO memory is always access though non-secure mapped virtual
addresses.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
H A Dstm32_rng.c68c4a16b37c797cf2a3d49af419f238e23cc8e4c Wed May 15 09:24:25 UTC 2019 Etienne Carriere <etienne.carriere@st.com> stm32mp1: use phys_to_virt_io_secure() where expected

This change updates platforms and drivers to use io_pa_or_va_secure()
when expecting a secure mapped address.

PWR, RCC, GIC, TAMP, BSEC, ETZPC, I2C are always secure (when embedded).

RNG uses a secure or non-secure mapping according to its registration in
platform shared_resource driver.

GPIOs IO memory is always access though non-secure mapped virtual
addresses.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
/optee_os/core/arch/arm/plat-stm32mp1/
H A Dmain.c68c4a16b37c797cf2a3d49af419f238e23cc8e4c Wed May 15 09:24:25 UTC 2019 Etienne Carriere <etienne.carriere@st.com> stm32mp1: use phys_to_virt_io_secure() where expected

This change updates platforms and drivers to use io_pa_or_va_secure()
when expecting a secure mapped address.

PWR, RCC, GIC, TAMP, BSEC, ETZPC, I2C are always secure (when embedded).

RNG uses a secure or non-secure mapping according to its registration in
platform shared_resource driver.

GPIOs IO memory is always access though non-secure mapped virtual
addresses.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>