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| /rk3399_rockchip-uboot/drivers/video/drm/ |
| H A D | rockchip_vop2.c | 67be2ffcf023cd75b5a7299a9fdfab736d3ad282 Fri Jan 14 10:06:19 UTC 2022 Damon Ding <damon.ding@rock-chips.com> drm/rockchip: vop2: fix the core_dclk_div_sel setting
When the display interface is BT656. the register of
core_dclk_div_sel should always be set 1. Not only 'i'
modes like 480i and 576i, but also 'p' modes like 720p,
both need this setting.
As for BT1120 and other interfaces, this bit should be
1 when display mode belongs to 'i', and 0 when display
mode belongs to 'p'.
Only RK3568 has the core_dclk_div_sel control bit, which
has been removed on RK3588.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: Ifdd3aef5541f4170eb5085da01a0820f1d713971
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