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| H A D | gpc.c | 66345b8b13dc32bcd9f6af3c04f60532e7d82858 Sun Jan 19 07:05:12 UTC 2020 Jacky Bai <ping.bai@nxp.com> feat(imx8mq): add 100us delay after USB OTG SRC bit 0 clear
After the SRC bit clear, we must wait for a while to make sure
the operation is finished. And don't enable all the PU domains
by default.
for USB OTG, the limitations are:
1. before system clock configuration. ipg clock runs at 12.5MHz.
delay time should longer than 82us.
2. after system clock configuration. ipg clock runs at 66.5MHz.
delay time should longer than 15.3us.
so add udelay 100 to safely clear the SRC bit 0.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I52e8e7739fdaaf86442bcd148e768b6af38bcdb7
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